Apparatus and method for testing memory cards

A first memory card comprising:

• a plurality of memory chips;
• one or more high-speed external card interfaces, including a first interface and a second interface, each connected to write and read data to and from the memory chips;
• and
• a test engine configured to control the first high-speed interface and the memory chips in order to provide testing functions to the second high-speed interface.

A memory-support circuit comprising:

• a system interface;
• a memory interface operable to generate read and write operations to a memory, wherein the circuit operates to provide data from the memory interface into the system interface;
• and
• a test engine operatively coupled to directly control the system interface and the memory interface in order to provide programmably configurable testing functions.

A memory-support circuit comprising:

• a system interface;
• a memory interface operable to generate read and write operations to a memory, wherein the circuit operates to provide data from the memory interface into the system interface;
• and
• a test engine operatively coupled to directly control the system interface and the memory interface in order to provide programmably configurable testing functions, and further comprising a control interface, wherein testing configuration information is loadable through the control interface into the test engine to provide the programmably configurable testing functions.

A memory-support circuit comprising:

• a system interface;
• a memory interface operable to generate read and write operations to a memory, wherein the circuit operates to provide data from the memory interface into the system interface;
• and
• a test engine operatively coupled to directly control the system interface and the memory interface in order to provide programmably configurable testing functions, and further comprising a cache operatively coupled to the memory interface and the system interface to provide cached data to the system interface.

A memory-support circuit comprising:

• a system interface;
• a memory interface operable to generate read and write operations to a memory, wherein the circuit operates to provide data from the memory interface into the system interface;
• and
• a test engine operatively coupled to directly control the system interface and the memory interface in order to provide programmably configurable testing functions, wherein the test engine includes:
• a test-generation function;
• and
• a test-result-checking function, wherein results can be returned and checked in an order different than the order in which they were generated.