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US 7,184,662 B2Granted
Switching network
AssigneeBay Microsysems, Inc.
InventorsYgal Arbel, Robert Louis Caulk, Christoph Dominique Loeffler-Lejeune
Life of this patent
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Abstract
A two-stage switching network that takes data from an input and first switches it through a space stage into a buffer. Data from the buffer is then switched in a time-space stage to an output. Each buffer, advantageously, holds one frame of data. Further, there are two buffers such that one may be filled from the input while the other is emptied to the output, and vice-versa. A maximum amount of data may be switched in space and time regardless of its origin and destination, effecting a switching network that is capable of the widest SONET-specified bandwidth.
Claims19
A switching network comprising:
- a first memory comprising 2x rows and y columns;
- a second memory comprising 2x rows and y columns;
- an x-to-2x demultiplexer configured to receive a first array of signals that comprises x rows of signals and y columns of signals and to switch, during a first stage, the signals only within each column of said first array to form a second array of signals in one of the first and second memories;
- and
- a 2x-to-x multiplexer configured to switch, during a second stage, the signals in said second array within both rows and columns to generate a third array of signals;
- wherein x and y are both positive integers greater than 1;
- and
- wherein to accomplish the switching;
- the x-to-2x demultiplexer writes into the first memory while the 2x-to-x multiplexer reads from the second memory, and
- the x-to-2x demultiplexer writes into the second memory while the 2x-to-x multiplexer reads from the first memory.
7 more elements
A method comprising:
- receiving a first frame of signals at an input pipeline, the first frame of signals comprising x rows of signals and y columns of signals;
- switching, via an x-to-2x demultiplexer, the first frame of signals only within each column to form a second array, wherein the switching comprises storing the second array in one of a first and second memory, and
- switching, via a 2x-to-x multiplexer, the signals within said second array within both rows and columns to form a third array at an output pipeline, wherein the switching comprises reading the second array from one of the first and second memories;
- wherein a frame of signals is stored in the first memory while a different frame of signals is read from the second memory;
- and
- wherein a frame of signals is stored in the second memory while a different frame of signals is read from the first memory.
3 more elements
A method for switching data comprising:
- in a first clock cycle;
- space switching a first set of data and writing the space switched first set of data to a first memory;
- and
- time and space switching a second set of data that was previously written into a second memory and reading the second set of data out of said second memory;
- in a second clock cycle;
- space switching a third set of data and writing the space switched third set of data into the second memory;
- and
- time and spare switching the first set of data that was written to the first memory in the first clock cycle and reading the first set of data out of the first memory.
5 more elements
A method for switching data comprising:
- in a first clock cycle;
- time and space switching a first set of data and writing the time and space switched first set of data to a first memory;
- and
- space switching a second set of data that was previously written into a second memory and reading the second set of data out of said second memory;
- in a second clock cycle;
- time and space switching a third set of data and writing the time and space switched third set of data into the second memory;
- and
- space switching the first set of data that was written to the first memory in the first clock cycle and reading the first set of data out of the first memory.
5 more elements
A two-stage switching element comprising:
- an input pipeline of data on an input side of a two-stage switching element;
- an output pipeline of data on an output side of the two-stage switching element;
- a first memory capable of storing a frame of data;
- a second memory capable of storing a frame of data;
- a demultiplexer configured to switch data from the input pipeline to the first and second memories;
- a multiplexer configured to switch data from the first and second memories to the output pipeline;
- a controller in signal communication with both the demultiplexer and the multiplexer and configured to generate read and write pointers which:
- during a first stage, 1) cause the demultiplexer to space switch a first frame from the input pipeline to the first memory, and 2) cause the multiplexer to time and space switch a second frame from the second memory to the output pipeline;
- and
- during a second stage, 1) cause the demultiplexer to space switch a third frame from the input pipeline to the second memory, and 2) cause the multiplexer to time and space switch the first frame from the first memory to the output pipeline.
7 more elements
A two-stage switching element comprising:
- an input pipeline of data on an input side of a two-stage switching element;
- an output pipeline of data on an output side of the two-stage switching element;
- a first memory capable of storing a frame of data;
- a second memory capable of storing a frame of data;
- a demultiplexer configured to switch data from the input pipeline to the first and second memories;
- a multiplexer configured to switch data from the first and second memories to the output pipeline;
- a controller in signal communication with both the demultiplexer and the multiplexer and configured to generate read and write pointers which:
- during a first stage, 1) cause the demultiplexer to time and space switch a first frame from the input pipeline to the first memory, and 2) cause the multiplexer to space switch a second frame from the second memory to the output pipeline;
- and
- during a second stage, 1) cause the demultiplexer to time and space switch a third frame from the input pipeline to the second memory, and 2) cause the multiplexer to space switch the first frame from the first memory to the output pipeline.
7 more elements
Dependencies are inferred from the claim text.