Layered decoding approach for low density parity check (LDPC) codes
AssigneeTexas Instruments Incorporated
InventorDale E. Hocevar
Life of this patent
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Abstract
A method of decoding in layers data received in a communication system, comprising receiving a codeword containing a plurality of elements and translating the plurality of elements into probability values by dividing the rows of at least one column of a parity check matrix associated with the codeword into groups and processing at least some of the groups separately.
Claims7
A method of decoding in layers data received in a communication system, comprising:
- receiving a codeword containing a plurality of elements, the codeword encoded according to a low density parity check code represented by a parity check matrix having rows and columns, each of the plurality of elements associated with a column of the parity check matrix, the columns of the parity check matrix corresponding to input nodes and the rows of the parity check matrix corresponding to parity check sums;
- dividing the rows of at least one column of the parity check matrix into groups;
- separately processing each of at least some of the groups by performing a sequence of operations comprising:
- for each row of the group, subtracting a previous check node value from a probability value for each input node contributing to the parity check sum for that row;
- generating a new check node value for that row using the result of the subtracting step;
- and
- for each input node contributing to the parity check sum for that row, updating a probability value using the new check node value and the result of the subtracting step;
- and
- then combining the updated probability values of the at least one column from each of the separately processed groups.
A system for decoding a received signal stream that was encoded according to a low density parity check code represented by a parity check matrix having rows and columns, each of the plurality of elements associated with a column of the parity check matrix, the columns of the parity check matrix corresponding to input nodes, comprising:
- a plurality of parallel computation blocks coupled to a memory;
- a plurality of parity check update blocks (PCUBs) coupled to said computation blocks, for updating check node values corresponding to participating input nodes for a row of the parity check matrix;
- and
- a plurality of column store blocks (CSBs) coupled to the PCUBs, each CSB comprising a memory for storing an updated probability value corresponding to a plurality of input nodes associated with each of a plurality of rows of the parity check matrix, each of the column store blocks comprising:
- a first memory portion for storing updated probability values for at least one input node associated with a first group of rows;
- a second memory portion for storing updated probability values for at least one input node associated with a second group of rows;
- and
- circuitry for combining updated probability values from the first and second memory portions for at least one input node.
Dependencies are inferred from the claim text.