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US 7,181,593 B2Granted
Active memory command engine and method
AssigneeMicron Technology, Inc.
InventorGraham Kirsch
Life of this patent
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Abstract
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.
Claims91
An integrated circuit active memory device fabricated on a single semiconductor substrate, the active memory device comprising:
- a memory device having a data bus containing a plurality of data bus bits;
- an array of processing elements with each processing element coupled to a respective group of the data bus bits, each of the processing elements having an instruction input coupled to receive processing element instructions for controlling the operation of the processing elements;
- an array control unit coupled to the processing elements in the array, the array control unit being operable to generate and to couple respective sets of the processing element instructions to the processing elements responsive to each of a plurality of array control unit commands applied to a command input of the array control unit;
- a memory device control unit coupled to the memory device, the memory device control unit being operable to generate and to couple respective sets of memory commands to the memory device responsive to each of a plurality of memory device control unit commands applied to a command input of the memory device control unit;
- and
- a command engine coupled to the array control unit and the memory device control unit, the command engine being operable to couple to the array control unit respective sets of the array control unit commands and to couple to the memory device control unit respective sets of the memory device control unit commands responsive to respective task commands applied to a task command input of the command engine.
3 more elements
An active memory control system, comprising:
- a first control device receiving task commands corresponding to respective active memory operations, the first control device being operable to generate either a respective set of memory commands or a respective set of processing commands responsive to each of the task commands, the processing commands being at a higher level than the respective task commands;
- a second control device coupled to receive the memory commands from the first control device, the second control device being operable to generate a respective set of the memory device instructions responsive to each of the memory commands;
- and
- a third control device coupled to receive the processing commands from the first control device, the third control device being operable to generate a respective set of the processing element instructions responsive to each of the processing commands.
1 more element
A computer system, comprising:
- a host processor having a processor bus;
- at least one input device coupled to the host processor through the processor bus;
- at least one output device coupled to the host processor through the processor bus;
- at least data storage device coupled to the host processor through the processor bus;
- and
- an active memory device, comprising:
- a memory device having a data bus containing a plurality of data bus bits;
- an array of processing elements with each processing element coupled to a respective group of the data bus bits, each of the processing elements having an instruction input coupled to receive processing element instructions for controlling the operation of the processing elements;
- an array control unit coupled to the processing elements in the array, the array control unit being operable to generate and to couple respective sets of the processing element instructions to the processing elements responsive to each of a plurality of array control unit commands applied to a command input of the array control unit;
- a memory device control unit coupled to the memory device, the memory device control unit being operable to generate and to couple respective sets of memory commands to the memory device responsive to each of a plurality of memory device control unit commands applied to a command input of the memory device control unit;
- and
- a command engine coupled to the array control unit and the memory device control unit, the command engine being operable to couple to the array control unit respective sets of the array control unit commands and to couple to the memory device control unit respective sets of the memory device control unit commands responsive to respective task commands applied to a task command input of the command engine from the host processor.
9 more elements
A method of controlling the operation of a memory device and an array of processing elements that are coupled to the memory device, the method comprising:
- receiving a task command corresponding to an active memory operation;
- responsive to the task command, generating either a set of array commands or a set of memory device commands;
- responsive to each of the array commands, generating a respective set of processing element instructions;
- responsive to each of the memory device commands, generating a respective set of memory device instructions;
- coupling the processing element instructions to the processing elements;
- and
- coupling the memory device instructions to the memory device.
4 more elements
An active memory control system, comprising:
- a first control device receiving task commands corresponding to respective active memory operations, the first control device being operable to generate either a respective set of memory commands or a respective set of processing commands responsive to each of the task commands, each of each of the task commands comprising:
- at least one device select bit that designates the task command as either a task command for the processing elements or a task command for the memory device, and
- a plurality of command data bits;
- a second control device coupled to receive the memory commands from the first control device, the second control device being operable to generate a respective set of the memory device instructions responsive to each of the memory commands;
- and
- a third control device coupled to receive the processing commands from the first control device, the third control device being operable to generate a respective set of the processing element instructions responsive to each of the processing commands.
3 more elements
An active memory control system, comprising:
- a first control device receiving task commands corresponding to respective active memory operations, the first control device being operable to generate either a respective set of memory commands or a respective set of processing commands responsive to each of the task commands, the first control device comprising an instruction cache storing a plurality of instructions at respective addresses, the instruction cache being programmable to allow sets of instructions to be stored in the cache based on the nature of the task commands that are received by the first control device;
- a second control device coupled to receive the memory commands from the first control device, the second control device being operable to generate a respective set of the memory device instructions responsive to each of the memory commands;
- and
- a third control device coupled to receive the processing commands from the first control device, the third control device being operable to generate a respective set of the processing element instructions responsive to each of the processing commands.
1 more element
An active memory control system, comprising:
- a first control device receiving task commands corresponding to respective active memory operations, the first control device being operable to generate either a respective set of memory commands or a respective set of processing commands responsive to each of the task commands, the first control device comprising:
- an arithmetic and logic unit;
- and
- a register coupled to receive and store data resulting from an arithmetic or logical operation performed by the arithmetic and logic unit;
- a second control device coupled to receive the memory commands from the first control device and the stored data from the register, the second control device being operable to generate a respective set of the memory device instructions responsive to each of the memory commands;
- and
- a third control device coupled to receive the processing commands from the first control device and the stored data from the register, the third control device being operable to generate a respective set of the processing element instructions responsive to each of the processing commands.
4 more elements
An active memory control system, comprising:
- a first control device receiving task commands corresponding to respective active memory operations, the first control device being operable to generate either a respective set of memory commands or a respective set of processing commands responsive to each of the task commands, the first control device comprising at least one defer buffer operable to store the memory commands and to subsequently output the memory commands;
- a second control device coupled to receive the memory commands from the at least one defer buffer in the first control device, the second control device being operable to generate a respective set of the memory device instructions responsive to each of the memory commands;
- and
- a third control device coupled to receive the processing commands from the first control device, the third control device being operable to generate a respective set of the processing element instructions responsive to each of the processing commands.
1 more element
An active memory control system, comprising:
- a first control device fabricated on an integrated circuit substrate, the first control device receiving task commands corresponding to respective active memory operations, the first control device being operable to generate either a respective set of memory commands or a respective set of processing commands responsive to each of the task commands, the processing commands being at a higher level than the respective task commands;
- a second control device fabricated on the integrated circuit substrate, the second control device being coupled to receive the memory commands from the first control device, the second control device being operable to generate a respective set of the memory device instructions responsive to each of the memory commands;
- and
- a third control device fabricated on the integrated substrate, the third control device being coupled to receive the processing commands from the first control device, the third control device being operable to generate a respective set of the processing element instructions respective to each of the processing commands.
1 more element
Dependencies are inferred from the claim text.