# US 7,180,775 B2 · Different numbers of bits per cell in non-volatile memory devices

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- Number: US 7,180,775 B2
- Document ID: US7180775B2
- Status: Granted
- Kind: B2
- Application number: 11/037,153
- Filed: 2005-01-19
- Published: 2006-02-09
- Granted: 2007-02-20
- Earliest claimed: 2004-08-05
- Assignees: Msystems Ltd.
- Inventors: Avraham Meir
- Web page: https://patentgrep.com/patent/US7180775B2

## CPC

- G11C 11/5621: {using charge storage in a floating gate}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method of manufacturing a non-volatile flash memory device, including setting a first number of bits stored per cell for at least one first cell less than a second number of bits stored per cell for at least one second cell such that the setting permanently fixes the first number and the second number prior to shipping the device for use. Preferably the setting is based on predicted reliabilities of the cells. Preferably, the predicted reliability of the first cells is less than the predicted reliability of the second cells. Preferably, the setting is based on respective locations within the device of the first cells and the second cells. Preferably, the setting is based on respective word lines connecting to the first cells and the second cells.

## Claims

### Claim 1

A method of manufacturing a non-volatile flash memory device, the method comprising the step of:
(a) setting a first number of bits stored per cell for at least one first cell less than a second number of bits stored per cell for at least one second cell;
wherein said setting permanently fixes said first number and said second number prior to shipping the device for use.

### Claim 2 (depends on 1)

The method, according to claim 1, wherein said setting is based on respective predicted reliabilities of said at least one first cell and said at least one second cell.

### Claim 3 (depends on 2)

The method, according to claim 2, wherein said predicted reliability of said at least one first cell is less than said predicted reliability of said at least one second cell.

### Claim 4 (depends on 1)

The method, according to claim 1, wherein said setting is based on respective locations within the device of said at least one first cell and said at least one second cell.

### Claim 5 (depends on 1)

The method, according to claim 1, wherein said setting is based on respective word lines connecting to said at least one first cell and said at least one second cell.

### Claim 6

A non-volatile flash memory device, having a first number of bits stored per cell for at least one first cell and having a second number of bits stored per cell for at least one second cell, wherein said first number is less than said second number;
wherein said first number and said second number are permanently fixed prior to shipping the device for use.

### Claim 7 (depends on 6)

The device, according to claim 6, wherein said first number and said second are based on respective predicted reliabilities of said at least one first cell and said at least one second cell.

### Claim 8 (depends on 7)

The device, according to claim 7, wherein said predicted reliability of said at least one first cell is less than said predicted reliability of said at least one second cell.

### Claim 9 (depends on 6)

The device, according to claim 6, wherein said first number and said second number are based on respective locations within the device of said at least one first cell and said at least one second cell.

### Claim 10 (depends on 6)

The device, according to claim 6, wherein said first number and said second number are based on word lines connecting respectively to said at least one first cell and said at least one second cell.

### Claim 11

A system for manufacturing a non-volatile flash memory device, the system comprising:
(a) the flash memory device including at least one first cell and at least one second cell;
wherein a first number of bits stored per cell of said at least one first cell is set less than a second number of bits stored per cell of said at least one second cell;
wherein said first number and said second number are permanently fixed prior to shipping the device for use.

### Claim 12 (depends on 11)

The system, according to claim 11, wherein said first number and said second are based on respective predicted reliabilities of said at least one first cell and said at least one second cell.

### Claim 13 (depends on 12)

The system, according to claim 12, wherein said predicted reliability of said at least one first cell is less than said predicted reliability of said at least one second cell.

### Claim 14 (depends on 11)

The system, according to claim 11, wherein said first number and said second number are based on respective locations within the device of said at least one first cell and said at least one second cell.

### Claim 15 (depends on 11)

The system, according to claim 11, wherein said first number and said second number are based on word lines connecting respectively to said at least one first cell and said at least one second cell.
