Process for production of SOI substrate and process for production of semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorTakeshi Fukunaga
Life of this patent
Estimating the term…
Abstract
A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands.
Claims10
A microprocessor comprising:
- a CPU,
- a cache memory,
- a cache controller,
- a RAM,
- a clock controller,
- a serial interface, and
- an IC, said IC comprising:
- a substrate having an insulating surface,
- a semiconductor film comprising silicon over said substrate, said semiconductor film including a channel region;
- a pair of LDD regions in said semiconductor film with said channel region therebetween wherein said pair of LDD regions contain an impurity of one conductivity type at a first concentration;
- a pair of impurity regions in said semiconductor film adjacent to said pair of LDD regions wherein said pair of impurity regions contain an impurity of the same conductivity type at a second concentration higher than said first concentration;
- a gate electrode over said channel region with a gate insulating film therebetween wherein said gate electrode partly overlaps each of said pair of LDD regions,
- side walls formed on side surfaces of said gate electrode, and
- wherein each of said pair of impurity regions comprises a metal silicide.
A microprocessor comprising:
- a CPU,
- a cache memory,
- a cache controller,
- a RAM,
- a clock controller,
- a serial interface, and
- an IC, said IC comprising:
- a substrate having an insulating surface,
- an underlying layer comprising aluminum nitride over said substrate,
- a semiconductor film comprising silicon over said underlying layer, said semiconductor film including a channel region;
- a pair of LDD regions in said semiconductor film with said channel region therebetween wherein said pair of LDD regions contain an impurity of one conductivity type a first concentration;
- a pair of impurity regions in said semiconductor film adjacent to said pair of LDD regions wherein said pair of impurity regions contain an impurity of the same conductivity type at a second concentration higher than said first concentration;
- a gate electrode over said channel region with a gate insulating film therebetween wherein said gate electrode partly overlaps each of said pair of LDD regions,
- side walls formed on side surface of said gate electrode, and
- wherein each of said pair of impurity regions comprises a metal silicide.
A microprocessor comprising:
- a CPU,
- a cache memory,
- a cache controller,
- a RAM,
- a clock controller,
- a serial interface, and
- an IC, said IC comprising:
- a substrate having an insulating surface,
- a semiconductor film comprising silicon over said substrate, said semiconductor film including a channel region;
- a pair of LDD regions in said semiconductor film with said channel region therebetween wherein said pair of LDD regions contain an impurity of one conductivity type a first concentration;
- a pair of impurity regions in said semiconductor film adjacent to said pair of LDD regions wherein said pair of impurity regions contain an impurity of the same conductivity type at a second concentration higher than said first concentration;
- a gate electrode over said channel region with a gate insulating film therebetween wherein said gate electrode partly overlaps each of said pair of LDD regions,
- side walls formed on side surface of said gate electrode,
- an interlayer insulating film comprising a resin over said gate electrode, and
- wherein each of said pair of impurity regions comprises a metal silicide.
Dependencies are inferred from the claim text.