US 7,174,224 B2Granted

Smart camera

AssigneeAdept Technology, Inc.

InventorsEdison T. Hudson, James McCormick, Ronald Genise, Jerome Dahl

Life of this patent

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Abstract

A smart camera system provides focused images to an operator at a host computer by processing digital images at the imaging location prior to sending them to the host computer. The smart camera has a resident digital signal processor for preprocessing digital images prior to transmitting the images to the host. The preprocessing includes image feature extraction and filtering, convolution and deconvolution methods, correction of parallax and perspective image error and image compression. Compression of the digital images in the smart camera at the imaging location permits the transmission of very high resolution color or high resolution grayscale images at real-time frame rates such as 30 frames per second over a high speed serial bus to a host computer or to any other node on the network, including any remote address on the Internet.

Claims4

Dependent claims

A method for distributed machine control, comprising:

controlling a first actuator with a first control module, said first module including a first processor carrying out a program of instructions and generating a first set of signals for controlling said first actuator;
controlling a second actuator with a smart camera module, said smart camera module including a second processor carrying out a program of instructions and generating a second set of signals for controlling said second actuator;
linking said first set of signals through a first error current block disposed in said first module to said first actuator, said first error current block receiving and transmitting an error current loop signal and interrupting said first set of signals if said error current loop signal is interrupted;
linking said second set of signals through a second error current block disposed in said smart camera module to said second actuator, said second error current block receiving and transmitting said error current loop signal and interrupting said second set of signals if said error current loop signal is interrupted;
detecting an error condition;
and
interrupting said error current loop signal upon detection of said error condition.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/922,984Filed 23 Aug 2004 · division
Priority: 10 Mar 2000
Published: US 2005/0021157 A127 Jan 2005
Granted: 6 Feb 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

G05B 19/0421
Using digital processors: multiprocessor system
G05B 2219/21053
Pc I-O input output: each unit, module has unique identification code, set during manufacturing, fMAC address
G05B 2219/23298
Pc programming: remote load of program, through internet
G05B 2219/23304
Pc programming: download program from host

Family

Application60/188,562Us provisional application · filed 10 Mar 2000
Application60/188,580Us provisional application · filed 10 Mar 2000
Application09/779,913Parent of this continuation-in-part · filed 7 Feb 2001
Application09/803,001Parent of this division · filed 9 Mar 2001
US 2005/0021157 A1Pre-grant publication · published 27 Jan 2005
US 6,988,008 B2Parent of this division
Application09/803,001Parent of this continuation-in-part
US 2001/0034557 A1Published application
US 2002/0051216 A1Published application
US 7,174,224 B2This patent

From the US filing history. Foreign family members aren’t listed.