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US 7,173,857 B2Granted
Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data
AssigneeRenesas Technology Corp.
InventorsHiroshi Kato, Yasuhiko Taito, Tsukasa Ooishi, Jun Ohtani
Life of this patent
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Abstract
At the time of an operation of writing data to a specific memory cell in a memory block, a semiconductor memory device applies a write voltage for a predetermined period and, after that, performs a verifying operation by using a sense amplifier circuit and a comparator. When it is found as a result of the verifying operation that writing to the memory cell is insufficient, the writing operation is performed again by an instruction of a memory control circuit. At this time, the memory control circuit adjusts a write voltage.
Claims4
A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate;
- a plurality of memory blocks including a plurality of nonvolatile memory cells arranged in a matrix;
- a plurality of word lines arranged in correspondence with a row direction of said plurality of memory cells;
- a plurality of bit lines arranged in correspondence with a column direction of said plurality of memory cells;
- and
- a control circuit for performing an erasing operation on said plurality of memory cells at the time of an erasing operation, wherein
- each of said plurality of memory cells includes:
- first and second conductive regions formed in a main surface of said semiconductor substrate and connected to corresponding bit lines in said plurality of bit lines;
- and
- an insulating film formed on said semiconductor substrate between said first and second conductive regions, having a first storing region in the vicinity of said first conductive region and a second storing region in the vicinity of said second conductive region, and
- said control circuit applies at least one pulse voltage to a selected memory cell in said plurality of memory cells,
- said nonvolatile semiconductor memory device further comprising a sense amplifier circuit for reading data stored in each of the plurality of memory cells, wherein
- said sense amplifier circuit is a single end type sense amplifier circuit, wherein
- said sense amplifier circuit further includes a reference potential generating circuit for generating said reference potential, and
- said reference potential generating circuit includes a plurality of reference cells operating at the time of a reading or erasing operation, wherein
- said plurality of reference cells include:
- a read reference cell operating in a reading operation;
- and
- an erase reference cell operating in an erasing operation and having a threshold value different from that of said read reference cell.
16 more elements
A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate;
- a plurality of memory blocks including a plurality of nonvolatile memory cells arranged in a matrix;
- a plurality of word lines arranged in correspondence with a row direction of said plurality of memory cells;
- a plurality of bit lines arranged in correspondence with a column direction of said plurality of memory cells;
- and
- a control circuit for performing an erasing operation on said plurality of memory cells at the time of an erasing operation, wherein
- each of said plurality of memory cells includes:
- first and second conductive regions formed in a main surface of said semiconductor substrate and connected to corresponding bit lines in said plurality of bit lines;
- and
- an insulating film formed on said semiconductor substrate between said first and second conductive regions, having a first storing region in the vicinity of said first conductive region and a second storing region in the vicinity of said second conductive region, and
- said control circuit applies at least one pulse voltage to a selected memory cell in said plurality of memory cells,
- said nonvolatile semiconductor memory device further comprising a sense amplifier circuit for reading data stored in each of the plurality of memory cells, wherein
- said sense amplifier circuit includes a differential amplifier circuit which receives data of each of said plurality of memory cells and a reference potential, wherein
- said sense amplifier circuit further includes a reference potential generating circuit for generating said reference potential, and
- said reference potential generating circuit includes a plurality of reference cells operating at the time of a reading or erasing operation, wherein
- said plurality of reference cells include:
- a read reference cell operating in a reading operation;
- and
- an erase reference cell operating in an erasing operation and having a threshold value different from that of said read reference cell.
16 more elements
Dependencies are inferred from the claim text.