Multiple-gate transistors formed on bulk substrates
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYee-Chia Yeo, Fu-Liang Yang, Chenming Hu
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Abstract
In one aspect, the present invention teaches a multiple-gate transistor 130 that includes a semiconductor fin 134 formed in a portion of a bulk semiconductor substrate 132. A gate dielectric 144 overlies a portion of the semiconductor fin 134 and a gate electrode 146 overlies the gate dielectric 144. A source region 138 and a drain region 140 are formed in the semiconductor fin 134 oppositely adjacent the gate electrode 144. In the preferred embodiment, the bottom surface 150 of the gate electrode 146 is lower than either the source-substrate junction 154 or the drain-substrate junction 152.
Claims36
A method of forming a multiple-gate transistor, the method comprising:
- providing a bulk semiconductor substrate;
- forming a semiconductor fin, in the bulk semiconductor substrate;
- forming isolation regions on sides of the semiconductor fin;
- forming a gate dielectric and a gate electrode on a portion of the semiconductor fin, the gate electrode having a bottom surface;
- after forming the gate electrode, forming a masking layer over the isolation region and covering a lower portion of the semiconductor fin;
- and
- forming a source region and a drain region in uncovered portions of the semiconductor fin, using the masking layer as a mask, the source region having a source-substrate junction and the drain region having a drain-substrate junction, the source-substrate junction or drain-substrate junction being higher than the bottom surface of the gate electrode by an amount based on a thickness of the masking layer.
The method of claim. 1 wherein the semiconductor fin comprises silicon.
A method of forming a semiconductor device, the method comprising:
- providing a silicon substrate;
- etching portions of the silicon substrate to form at least one semiconductor fin;
- forming a gate dielectric layer over the semiconductor fin;
- forming a gate electrode layer over the gate dielectric layer;
- etching portions of the gate electrode layer to form a gate electrode, the gate electrode overlying sidewalls and a top surface of the semiconductor fin;
- after etching portions of the gate electrode layer, forming a region of material adjacent portions of the semiconductor fin not underlying the gate electrode such that a sidewall of the semiconductor fin extends above an upper surface of the region of material;
- and
- after forming the region of material, doping the sidewall of the semiconductor fin above the region of material.
Dependencies are inferred from the claim text.