Frequency agile tuner and variable rate decimator for digital demodulator

A method for demodulating a digital input signal having a pre-assigned symbol rate by using a single sample clock signal;

• said pre-assigned symbol rate is selected from the group consisting of a plurality of symbol rates;
• said method comprising the steps of:
• down converting an input digital signal having said pre-assigned symbol rate from a carrier frequency to a baseband frequency by using a Complex Mixer;
• performing a filtering-decimation operation by using a Cascaded Integrated Comb (CIC) Decimator filter in order to isolate a down converted digital signal having said pre-assigned symbol rate;
• generating a CIC_output_signal having a CIC-shaped decimated spectrum by using said (CIC) Decimator filter;
• restoring an original spectrum of said CIC_output_signal having said CIC-shaped decimated spectrum by using a Shaper filter, wherein an I component and Q component of a shaper_filter_output_signal include a shaper_signal component having said restored original spectrum of said pre-assigned signal and include an adjacent shaper-signal component having a spectrum that is adjacent to said restored original spectrum of said pre-assigned signal;
• using a CIC cutoff filter to pass said shaper_signal component having a restored original spectrum of said pre-assigned signal and to pass a part of said adjacent signal having a spectrum part that is carved out by a frequency response function of said CIC cutoff filter;
• demodulating and extracting a frequency component from said shaper_signal component having said restored original spectrum of said pre-assigned signal by using a Demodulator;
• estimating a frequency offset between said pre-assigned carrier frequency and said frequency component of said shaper_signal component having said restored original spectrum of said pre-assigned signal by using a Coarse Frequency estimation block;
• and
• completing a carrier recovery of said pre-assigned input digital signal by inserting said estimated by said Coarse Frequency estimation block frequency offset into a carrier loop by using a CIC tuner loop filter.

An apparatus for demodulating a digital input signal having a pre-assigned symbol rate by using a single sample clock signal;

• said pre-assigned symbol rate is selected from the group consisting of a plurality of symbol rates;
• said apparatus comprising:
• a means for down converting an input digital signal having said pre-assigned symbol rate signal from a carrier frequency to a baseband frequency;
• a means for performing a filtering-decimation operation to isolate a down converted digital signal having said pre-assigned symbol rate;
• wherein said means for performing said filtering-decimation operation to isolate said down converted digital signal having said pre-assigned symbol rate further includes:
• an integer K of parallel Cascaded Integrated Comb CIC integrators;
• an integer K of Numerical Control Oscillators (NCO)s;
• and
• an integer K of CIC mixers;
• wherein a K-stage integrator is configured to increase by a K-factor a processing speed of said incoming digital input signal having said pre-assigned data rate;
• a means for restoring an original spectrum of a pre-assigned signal;
• a means for extracting a frequency component from a restored signal having said original spectrum of said pre-assigned signal;
• a means for estimating a frequency offset between a pre-assigned carrier frequency and said frequency component of said restored signal having said original spectrum of said pre-assigned signal;
• and
• a means for inserting said estimated frequency offset into a carrier loop in order to complete a carrier recovery of said pre-assigned input digital signal;