US 7,170,347 B1Granted

Offset trim circuit and method for a constant-transconductance rail-to-rail CMOS input circuit

AssigneeNational Semiconductor Corporation

InventorWillem Johannes Kindt

Life of this patent

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Abstract

A constant-transconductance rail-to-rail CMOS input circuit with offset trim is provided. PMOS and NMOS differential trim stages are scaled versions of PMOS and NMOS input stages respectively. The differential trim stages are configured to adjust the offset of the differential output current with accuracy over temperature. A first current mirror circuit is configured to receive a fraction of a bias current (βI), where β is related to the input common mode voltage. A second current mirror circuit is configured to receive another fraction of the bias current ((1−β)I). The first current mirror circuit is configured to provide current βI to the PMOS input stage, and a scaled-down version of current βI to the PMOS differential trim stage. The second current mirror circuit is configured to provide current ((1−β)I) to the NMOS input stage, and a scaled-down version of current ((1−β)I) to the differential PMOS trim stage.

Claims22

Dependent claims

An input circuit that is arranged for rail-to-rail operation with a differential input signal, comprising:

a differential input circuit for receiving the differential input signal, wherein the differential input circuit is configured to provide:
a first positive differential current in response to the differential input signal, and
a first negative differential current in response to the differential input signal;
a differential trim circuit for enabling trimming of an offset, wherein the differential trim circuit is configured to provide:
a second positive differential current in response to a differential positive trim signal;
and
a second negative differential current in response to a differential negative trim signal;
and
a current mirror stage for enabling a transconductance of the input circuit to be relatively constant for a common mode voltage of the differential input signal, comprising:
a first current mirror circuit that is configured to receive a first current that is related to the common mode voltage, wherein the first current mirror circuit is further configured to reflect the first current to provide a first positive tail current to the differential input circuit, and further configured to reflect the first current to provide a second positive tail current to the differential trim circuit;
and
a second current mirror circuit that is configured to receive a second current that is related to the common mode voltage, wherein the second current mirror circuit is further configured to reflect the second current to provide a first negative tail current to the differential input circuit, and further configured to reflect the first current to provide a second negative tail current to the differential trim circuit;
and
an output stage for providing differential output currents.

11 more elements

A CMOS input circuit that is arranged for rail-to-rail operation with a differential input signal, comprising:

a differential input circuit for receiving the differential input signal, comprising:
a PMOS differential input stage that is arranged to provide a first PMOS differential current in response to the differential input signal;
and
an NMOS differential input stage that is arranged to provide a first NMOS differential current in response to the differential input signal;
a differential trim circuit for enabling trimming of an offset, comprising:
a PMOS differential trim stage that is arranged to provide a second PMOS differential current in response to a differential PMOS trim signal;
and
an NMOS differential trim stage that is arranged to provide a second NMOS differential current in response to a differential NMOS trim signal;
and
a current mirror stage for enabling a transconductance of the input circuit to be relatively constant for a common mode voltage of the differential input signal, comprising:
a first current mirror circuit that is configured to receive a first current that is related to the common mode voltage, wherein the first current mirror circuit is further configured to reflect the first current to provide a first PMOS tail current to the PMOS differential input stage, and further configured to reflect the first current to provide a second PMOS tail current to the PMOS differential trim stage;
and
a second current mirror circuit that is configured to receive a second current that is related to the common mode voltage, wherein the second current mirror circuit is further configured to reflect the second current to provide a first NMOS tail current to the NMOS differential input stage, and further configured to reflect the first current to provide a second NMOS tail current to the NMOS differential trim stage;
and
an output stage for enabling the first PMOS differential current and the second PMOS differential current to be combined to provide a PMOS differential output current, and further enabling the first NMOS differential current and the second NMOS differential current to be combined to provide a NMOS differential output current.

12 more elements

A method employing an input circuit to provide differential output current in response to a differential input signal, the method comprising:

receiving the differential input signal via a rail-to-rail CMOS input stage;
trimming an offset of the differential input signal such that accuracy over temperature is approximately maintained;
and
enabling a transconductance of the input circuit to be relatively constant for a common mode voltage of the differential input signal.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 10/716,019Filed 17 Nov 2003
Granted: 30 Jan 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs
H03F 3/45695
In differential amplifiers with FET transistors as the active amplifying circuit: by using feedforward means
H03F 2200/456
Indexing scheme relating to amplifiers: a scaled replica of a transistor being present in an amplifier
H03F 2203/45366
Indexing scheme relating to differential amplifiers: the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a…