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US 7,169,675 B2Granted
Material architecture for the fabrication of low temperature transistor
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsChung Foong Tan, Jinping Liu, Hyeokjae Lee, Kheng Chok Tee, Elgin Quek
Life of this patent
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Abstract
A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
Claims49
A method to form first and second regions and a carbon containing layer using implantation processes in a substrate comprising:
- a) forming a carbon containing layer in a substrate;
- said carbon containing layer has a carbon concentration between 5E18 and 1E20 atom/cc;
- b) implanting ions to form a first region and a first end-of-range region in the substrate;
- (1) at least a portion of said first end-of-range region is in said carbon containing layer,
- said first end-of-range region is at least at a depth between 1.0*Rp-first region and 1.5*Rp-first region;
- c) implanting ions to form a second region and a second end-of-range region in the substrate;
- (1) at least a portion of said second region end-of-range region is in said carbon containing layer;
- said carbon containing layer extends at least from the 1.0 * Rp of the first region to 1.5*Rp of the second region;
- step b and step c are two separate different implant steps.
6 more elements
A method to form a low temperature MOSFET using a carbon doped region comprising:
- a) forming a carbon containing layer in or on a substrate;
- said substrate comprised of a crystalline silicon;
- b) forming a gate structure over said substrate;
- a channel region in said substrate under said gate structure;
- c) implanting ions to form pocket regions and pocket EOR regions;
- (1) said pocket regions at least partially in said substrate and said carbon containing layer,
- (2) said pocket EOR regions have a depth at least between 1.0*Rppocket and 1.5 * Rppocket;
- (3) said pocket EOR regions in said carbon containing layer,
- d) forming S/D extension regions in said substrate adjacent said gate structure;
- e) forming spacers on the sidewalls of said gate structure,
- f) implanting ions to form source/drain regions and source/drain end-of-range regions in said substrate adjacent said gate structure;
- (1) said source/drain regions formed by an ion implant process where the source/drain end-of-range regions are within said carbon containing layer,
- g) annealing said substrate whereby the carbon containing layer acts as a sink for defects.
10 more elements
A method to form a low temperature MOSFET using a carbon doped region comprising:
- a) forming a carbon containing layer on a substrate;
- said substrate comprised of a crystalline silicon;
- (1) said carbon containing layer formed by a growth method selected from chemical vapor deposition or epitaxy growth;
- b) forming a silicon layer over said carbon containing layer,
- c) forming a gate structure on said silicon layer, a channel region in said silicon layer under said gate structure;
- d) implanting ions to form pocket regions and pocket EOR regions in said substrate;
- (1) said pocket regions at least partially in said substrate and at least partially in said carbon containing layer;
- e) forming S/D extension regions in said silicon epitaxy layer adjacent said gate structure;
- f) forming spacers on the sidewalls of said gate structure;
- g) implanting ions to form source/drain regions and source/drain EOR regions in said silicon layer adjacent said gate structure;
- (1) said source/drain regions formed by an ion implant process where said source/drain EOR regions are within said carbon containing layer;
- h) annealing said substrate whereby the carbon containing layer acts as a sink for defects from the pocket implant and source/drain implant.
9 more elements
A method to form a low temperature MOSFET using a carbon doped region comprising:
- a) forming a strained region over the substrate;
- b) forming a carbon containing layer over the strained region;
- c) forming a silicon cap layer over said carbon containing layer,
- d) forming a gate structure over said substrate;
- a channel region under said gate structure;
- e) implanting ions to form pocket regions, and pocket EOR regions in said substrate structure;
- (1) said pocket regions at least partially in said substrate and said carbon containing layer,
- (2) said pocket EOR regions in said carbon containing layer,
- f) forming S/D extension regions in said substrate adjacent said gate structure;
- g) forming spacers on the sidewalls of said gate structure;
- h) implanting ions to form source/drain regions and source/drain end-of-Range regions in said substrate structure adjacent said gate structure;
- (1) said source/drain regions formed by an ion implant process where the source/drain end-of-range regions are within said carbon containing layer,
- i) annealing said substrate whereby the carbon containing layer acts as a sink for defects.
10 more elements
A method for forming implanted C-regions in a semiconductor device comprising the steps of:
- a) forming a gate structure on said silicon layer, a channel region in a substrate under said gate structure;
- b) implanting ions to form pocket regions and pocket EOR regions in said substrate;
- c) implanting C ions into said substrate in said pocket EOR regions to form carbon-containing pocket EOR regions;
- said pocket EOR regions in said carbon-containing pocket EOR regions;
- d) forming SDE regions and SDE EOR regions in said substrate adjacent said gate structure;
- e) implanting C ions into said substrate in said SDE EOR regions to form carbon-containing SDE EOR regions;
- said SDE EOR regions in said carbon-containing SDE EOR regions;
- f) forming spacers on the sidewalls of said gate structure;
- g) forming source/drain regions and source/drain EOR regions in said substrate under said gate structure;
- h) implanting C ions into said substrate in said source/drain end-of-range regions to form carbon-containing source/drain EOR regions;
- said source/drain end-of-range regions in said carbon-containing source/drain EOR regions;
- (1) said carbon-containing source/drain EOR regions have a carbon concentration between 5E18 and 1E20 atom/cc;
- and
- (2) said carbon-containing source/drain EOR regions are positioned at a depth between 1.0 times the depth of the projected range of the source-drain regions and 2.0 times the depth of the projected range of the source-drain regions;
- i) annealing said substrate whereby the carbon containing layers act as a sink for defects from the pocket implant, the SDE implant and source/drain implant;
- (1) the projected range and end-or-range regions for the pocket implant, the SDE implant and the source/drain implant are in the carbon containing layers.
13 more elements
A method for forming implanted C-regions in a semiconductor device comprising the steps of:
- a) forming a gate structure on a substrate;
- a channel region in said substrate under said gate structure;
- b) implanting dopant ions to form pocket regions and pocket EOR regions in said substrate;
- c) implanting C ions into said substrate in said pocket EOR regions to form carbon-containing pocket EOR regions;
- said pocket EOR regions are in said carbon-containing pocket EOR regions;
- steps b) and c) are distinct implant steps;
- said carbon-containing pocket EOR regions have a carbon concentration between 5E18 and 1E20 atom/cc;
- d) forming SDE regions and SDE EOR regions in said substrate adjacent said gate structure;
- e) forming spacers on the sidewalls of said gate structure;
- f) forming source/drain regions and source/drain end-of-range regions in said substrate under said gate structure;
- g) annealing said substrate whereby the carbon containing layers act as a sink for defects.
8 more elements
A method for forming implanted C-regions in a semiconductor device comprising the steps of:
- a) forming a gate structure on a substrate;
- a channel region in said substrate under said gate structure;
- b) implanting ions to form pocket regions and pocket EOR regions in said substrate;
- c) forming SDE regions and SDE EOR regions in said substrate adjacent said gate structure;
- d) implanting C ions into said substrate in said SDE EOR regions to form carbon-containing SDE EOR regions;
- said SDE EOR regions in said carbon-containing SDE EOR regions;
- said carbon-containing SDE EOR regions are positioned at a depth between 1.0 times the depth of the projected range ofthe SDE regions and 2.0 times the depth of the projected range ofthe SDE regions;
- said carbon containing SDE EOR regions have a carbon concentration between 5E18 and 1E20 atom/cc;
- e) forming spacers on the sidewalls of said gate structure;
- f) forming source/drain regions and source/drain end-of-range regions in said substrate under said gate structure;
- g) annealing said substrate whereby the carbon containing layers act as a sink for defects from the SDE implant.
8 more elements
A method for forming implanted C-regions in a semiconductor device comprising the steps of:
- a) forming a gate structure over a substrate;
- a channel region in said substrate under said gate structure;
- b) implanting ions to form pocket regions and pocket EOR regions in said substrate;
- c) forming SDE regions in said substrate adjacent said gate structure;
- d) forming spacers on the sidewalls of said gate structure;
- e) forming source/drain regions and source/drain EOR regions in said substrate under said gate structure;
- f) implanting C ions into said substrate in said source/drain EOR regions to form carbon-containing source/drain EOR regions;
- said source/drain EOR regions in said carbon-containing source/drain EOR regions;
- (1) said carbon-containing source/drain EOR regions have a carbon concentration between 5E18 and 1E20 atom/cc;
- and
- (2) said carbon-containing source/drain EOR regions are positioned at a depth between 1.0 times the depth of the projected range of the source-drain regions and 2.0 times the depth of the projected range of the source-drain regions;
- g) annealing said substrate whereby the carbon containing layers act as a sink for defects from the pocket implant, the SDE implant and source/drain implant.
9 more elements
The method of implanting a carbon-containing layer in the EOR region of a PAI implant for a SDE region comprising the steps of:
- a) forming a gate structure over a substrate;
- b) performing a PAI implant to implant a non-dopant to form PAI regions and PAI end-of-range regions;
- c) implanting C to form C-containing PAI layers;
- said PAI end-of-range regions are in said C-containing PAI layers;
- steps b) and c) are two separate and distinct implantations:
- said C-containing PAI layers have a carbon concentration between 5E18 and 1E20 atom/cc:
- d) performing a SDE implant to form SDE regions;
- e) annealing said substrate.
5 more elements
Dependencies are inferred from the claim text.