Programmable transition state machine
AssigneeTexas Instruments Incorporated
InventorsRoshan J. Samuel, Jason D. Kridner
Life of this patent
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Abstract
The programmable transition state machine of this invention is designed to allow implementation of hardware capable of increasing the performance of critical encoding and decoding tasks in a microprocessor environment where a required encoding or decoding or machines is not known in advance. The state machine described may also be used in systems that need flexibility to support a wide variety of functions or machines or where a hardwired approach is not useful. This unique state machine processes the state information and the transition from a present state to a next state in CPU-programmable logic.
Claims12
A programmable Mealy state machine comprising:
- a header pattern buffer receiving input header parameter information and generating a starting address corresponding to data input and a match signal when a data input matches a header pattern stored therein;
- a programmable state transition memory having stored states at locations corresponding to said starting addresses, a next state derived from said stored state at said location corresponding to said starting address;
- a next state control circuit connected to said header pattern buffer and controlling said programmable state transition memory for a predetermined plural number of cycles;
- and
- an output device generating an output upon receipt of a next state from said programmable state transition memory.
A programmable Mealy state machine comprising:
- a header pattern buffer receiving input header parameter information and generating a starting address corresponding to data input and a match signal when a data input matches a header pattern stored therein;
- a programmable state transition memory having stored states at locations corresponding to said starting addresses, a next state derived from said stored state at said location corresponding to said starting address;
- a next state control circuit connected to said header pattern buffer and controlling said programmable state transition memory for a predetermined number of cycles, said next state control circuit including a programmable counter loaded with said predetermined number, said programmable counter started upon receipt of said match signal and halting further transitions of said programmable state transition memory upon expiration of said predetermined number of cycles;
- and
- an output device generating an output upon receipt of a next state from said programmable state transition memory.
Dependencies are inferred from the claim text.