US 7,159,002 B2Granted

Biquad digital filter operating at maximum efficiency

AssigneeTexas Instruments Incorporated

InventorSrikanth Gurrapu

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Abstract

An architecture for a biquad (70), second-order infinite impulse response (IIR) digital filter, that is capable of operating at maximum efficiency, is disclosed. The biquad (70) includes coefficient memory (50) and data memory (52), along with control circuitry (53) that loads values from these memories (50, 52) into a coefficient register (52) and a data register (54), respectively. A multiplier (55) multiplies the values in the coefficient register (52) and data register (54), with the resulting product being stored in a product register (58). An accumulator (59) adds successive product results to derive a new output value in each instance of the IIR filter. A shadow register (60) temporarily stores the output of the accumulator (59) from a previous instance, permitting this output to be stored in the data memory (52) at a later time in the sequence. This permits the order of operations in the second and successive biquads to be altered so that each successive biquad instance can start well before the previous result is derived; as a result, the multiplier (55) is fed with values each cycle, enabling maximum efficiency operation.

Claims28

Dependent claims

A method of performing a sequence of infinite impulse response digital filters, comprising the steps of:

in a first instance of the filter, executing a series of operations comprising:
sequentially multiplying a current input data value, and first and second previous input data values, with corresponding ones of a first set of filter coefficients, using a multiplier;
sequentially multiplying first and second previous intermediate data values with corresponding ones of the first set of filter coefficients, using the multiplier;
and
sequentially accumulating products from each multiplying operation into an accumulator;
in a second instance of the filter, executing a series of operations comprising:
in a same clock cycle as a next to last one of the sequential accumulating operations, multiplying the second previous intermediate data value with a corresponding one of a second set of filter coefficients, using the multiplier;
in a next clock cycle, then loading the contents of the accumulator into a shadow store and multiplying the contents of the accumulator with a corresponding one of the second set of filter coefficients, using the multiplier;
then clearing the accumulator;
sequentially multiplying the first previous intermediate data value with a corresponding one of a second set of filter coefficients, and multiplying first and second previous output data values with corresponding ones of the second set of filter coefficients;
and
then sequentially accumulating products from each multiplying operation in the second instance of the filter in the accumulator;
and
storing the contents of the shadow store in memory.

11 more elements

A digital audio processor, comprising:

an input channel mixer, for receiving a plurality of audio signal input channels;
a plurality of digital signal processing channels, each for processing one of the plurality of audio signal input channels received by the input channel mixer, each comprising:
digital filter circuitry for performing a sequence of infinite impulse response digital filters, comprising:
memory, for storing a plurality of sets of filter coefficients, and for storing data values corresponding to input and output datastreams;
a coefficient store, for storing a selected filter coefficient;
a data store, for storing a selected data value;
a multiplier, having inputs coupled to the coefficient and data stores, for multiplying the selected filter coefficient with the selected data value;
a product store, having an input coupled to the multiplier, for storing the product of the selected filter coefficient with the selected data value;
an accumulator, having an input coupled to the product store, for adding product values from the product store;
a shadow store, having an input coupled to the output of the accumulator, and having an output coupled to the memory;
and
control circuitry, for loading the contents of the accumulator into the data store and the shadow store, and for then clearing the contents of the accumulator, in a speedup operation, so that the multiplier then multiplies the previous contents of the accumulator with a selected coefficient following the speedup operation;
and
an audio output crossbar, for routing output values from the plurality of digital signal processing channels audio outputs.

11 more elements

A digital audio processor, comprising:

an input channel mixer, for receiving a plurality of audio signal input channels;
a plurality of digital signal processing channel circuits, each for processing one of the plurality of audio signal input channels received by the input channel mixer, each digital signal processing channel circuit including circuitry programmed to perform a plurality of instances of a digital filter in sequence by executing a plurality of operations comprising:
in a first instance of the filter, executing a series of operations comprising:
sequentially multiplying a current input data value, and first and second previous input data values, with corresponding ones of a first set of filter coefficients, using a multiplier;
sequentially multiplying first and second previous intermediate data values with corresponding ones of the first set of filter coefficients, using the multiplier;
and
sequentially accumulating products from each multiplying operation into an accumulator;
in a second instance of the filter, executing a series of operations comprising:
in a same clock cycle as a next to last one of the sequential accumulating operations, multiplying the second previous intermediate data value with a corresponding one of a second set of filter coefficients, using the multiplier;
in a next clock cycle, then loading the contents of the accumulator into a shadow store and multiplying the contents of the accumulator with a corresponding one of the second set of filter coefficients, using the multiplier;
then clearing the accumulator;
sequentially multiplying the first previous intermediate data value with a corresponding one of a second set of filter coefficients, and multiplying first and second previous output data values with corresponding ones of the second set of filter coefficients;
and
then sequentially accumulating products from each multiplying operation in the second instance of the filter in the accumulator;
and
storing the contents of the shadow store in memory;
and
an audio output crossbar, for routing output values from the plurality of digital signal processing channels audio outputs.

15 more elements

Dependencies are inferred from the claim text.