Digital frequency difference detector with inherent low pass filtering and lock detection
AssigneeSeiko Epson Corporation
InventorDavid Meltzer
Life of this patent
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Abstract
A structure and method for implementing a fully digital frequency difference detector uses an n-bit counter to count cycles of a reference clock signal and an m-bit counter to count cycles of a synthesized clock signal, where m is greater than n. The two counters operate concurrently, and both are halted when the n-bit counter overflows into its nth bit position. Two latches respectively record if bits n and (n+1) in the m-bit become set prior to the n-bit counter overflowing. By observing the state of the two latches and the state of a predefined bit range within the m-counter, the frequency difference detector can determined if the frequency of the synthesized clock is greater than, less than, or locked to the frequency of the reference clock signal.
Claims20
A frequency difference detector for detecting the frequency difference between first and second signals, comprising:
- a first input for receiving said first signal;
- a second input for receiving said second signal;
- a first counter configured to count pulses of the first input signal;
- a second counter configured to count pulses of the second input signal, said second counter being capable of a higher bit count than said first counter;
- a first memory for storing a logic value indicating that said second counter has overflowed out of a first bit position in response to said second counter overflowing out of said first bit position;
- a second memory for storing a logic value indicating that said second counter has overflowed out of a second bit position in response to said second counter overflowing out of said second bit position;
- and
- a logic circuit effective for responding to said first counter overflowing out of its corresponding first bit position, by examining the current bit value of the second counter and the stored logic values said first and second memories and determining from theses examined values if said first signal has a higher frequency than said second signal.
A digital frequency difference detector, comprising:
- a first frequency detection input for receiving a first signal;
- a second frequency detection input for receiving a second signal;
- an n-bit counter for counting pulses received at said first frequency-detection input, whereby said n-bit counter maintains a pulse-count of said first signal;
- an m-bit counter for counting pulses received at said second frequency detection input, whereby said m-bit counter maintains a pulse-count of said second signal, and wherein m is greater than n;
- a first memory cell for storing a SET condition in response to the nth bit within said m-bit counter transitioning into a first logic state and for maintaining said SET condition irrespective of said nth bit within said m-bit counter transitioning out of said first logic state;
- a second memory cell for storing a SET condition in response to the (n+1)th bit within said m-bit counter transitioning into said first logic state and for maintaining said SET condition irrespective of said (n+1)th bit transitioning out of said first logic state;
- wherein said n-bit counter and said m-bit counter are halted in response to the nth bit within said n-bit counter transitioning into said first logic state;
- and
- wherein upon said halting of said n-bit and m-bit counters, said digital frequency difference detector determines:
- a) that the frequency of said second signal is lower than said first signal if neither of said first or second memory cells have said SET condition stored;
- or
- b) that the frequency of said second signal is higher than said first signal if said second memory cell has said SET condition stored;
- or
- c) that the frequency of said second signal is higher than said first signal if said first memory cell has said SET condition stored and any bit within said m-bit counter excluding a predetermined number of least significant bits is set to said first logic state;
- or
- d) that the frequency of said second signal is locked to said first signal if said first memory cell has said SET condition stored and said second memory cell does not have said SET condition stored and no bit within said m-bit counter excluding said predetermined number of least significant bits is set to said first logic state.
A method for detecting a frequency difference between a first signal and a second signal, said method comprising:
- monitoring said first signal to count pulses in said first signal up to a first predetermined value;
- monitoring said second signal to count pulses in said second signal;
- when the pulse count of said first signal reaches said predetermined value, comparing said predetermined value with a current pulse count of said second signal, and determining:
- a) that a frequency of the second signal is lower than the frequency of the first signal if the predetermined value is greater than the pulse count of the second signal by an amount greater than a predefined margin;
- or
- b) that the frequency of the second signal is greater than the frequency of the first signal if the predetermined value is less than the pulse count of the second signal by an amount greater than said predefined margin;
- and
- c) that the frequency of the second signal is locked to the frequency of the first signal if magnitude of the difference between the predefined value and the pulse count of the second signal is within said predefined margin.
Dependencies are inferred from the claim text.