Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation

A method of simulating a control-dataflow graph comprising:

• building an internal representation of the control-dataflow graph emulating reconfigurable logic for a reconfigurable processor implemented algorithm comprising a current block;
• sending a trigger token to the current block, wherein said trigger token initiates execution of the current block in its entirety, wherein execution of the current block progresses from the top of the current block to the bottom of the current block;
• providing a plurality of LOAD nodes at the top of the current block for loading the current values of an executing program's variables;
• feeding values from the LOAD nodes into a computational portion of the control-dataflow graph;
• providing a plurality of STORE nodes at the bottom of the current block for receiving the results of the computational portion of the control-dataflow graph and for storing updated values of the executing program's variables;
• producing an output value of the current block, wherein the output value determines subsequent block execution, wherein, except for the output value that determines subsequent block execution, the current block and each subsequent block are independent control-dataflow representations that lack any data connection between the respective control-dataflow graph representations;
• and
• thereafter terminating the current block.