Delay stage-interweaved analog DLL/PLL

A memory device, comprising:

• a plurality of memory cells to store data;
• and
• a plurality of peripheral devices for writing data into and reading data out of said plurality of memory cells, said plurality of peripheral devices including a delay locked loop configured to provide a clock signal having a predetermined phase relationship with a reference clock input thereto to facilitate a data read/write operation at one or more of said plurality of memory cells, wherein said delay locked loop includes:
• a voltage controlled delay line (VCDL) receiving said reference clock as an input thereto and including a plurality of delay stages to delay said reference clock, wherein said VCDL is configured to apply said reference clock and an externally received bias signal to each of said plurality of delay stages to generate one of a plurality of output signals at a corresponding output of each of said plurality of delays stages, wherein each of said plurality of output signals is a correspondingly delayed version of said reference clock;
• and
• a detection unit connected to said VCDL to receive a subset of said plurality of output signals and to generate a set of detection signals based on a phase relation between one or more pairs of output signals in said subset of output signals, wherein said detection unit is configured to send said set of detection signals to said VCDL to enable said VCDL to disable one or more of said plurality of delay stages using said set of detection signals.

A system, comprising:

• a processor;
• a bus;
• and
• a memory device coupled to said processor via said bus, wherein said memory device includes:
• a plurality of memory cells to store data;
• and a plurality of peripheral devices for writing data into and reading data out of said plurality of memory cells, said plurality of peripheral devices including a synchronous circuit configured to provide a clock signal having a predetermined phase relationship with a reference clock input thereto to facilitate a data read/write operation at one or more of said plurality of memory cells, wherein said synchronous circuit includes:
• a voltage controlled delay line (VCDL) receiving said reference clock as an input thereto and including a plurality of delay stages to delay said reference clock, wherein said VCDL is configured to apply said reference clock and an externally received bias signal to each of said plurality of delay stages to generate one of a plurality of output signals at a corresponding output of each of said plurality of delays stages, wherein each of said plurality of output signals is a correspondingly delayed version of said reference clock;
• and
• a detection unit connected to said VCDL to receive a subset of said plurality of output signals and to generate a set of detection signals based on a phase relation between one or more pairs of output signals in said subset of output signals, wherein said detection unit is configured to send said set of detection signals to said VCDL to enable said VCDL to disable one or more of said plurality of delay stages using said set of detection signals.