Circuitry and methods for efficient FIFO memory
AssigneeMarvell Semiconductor Israel Ltd.
InventorEitan Rosen
Life of this patent
Estimating the term…
Abstract
Circuitry and methods for an efficient FIFO memory are provided. This efficient FIFO memory has two smaller standard single-port memory banks instead of one large dual-port memory bank, as in typical FIFO memories. Whereas the dual-port memory based FIFO memory can read and write data at the same time, a typical single-port memory based FIFO cannot. The operation of the two single-port memory banks are coordinated in order to provide similar or better performance than a dual-port memory based FIFO.
Claims30
A method of providing an efficient FIFO memory comprising:
- receiving data having a plurality of portions;
- alternately writing said data to a first memory and a second memory;
- and
- alternately reading said data from said first memory and said second memory, wherein alternately reading said data comprises alternately writing said data to a first data register and a second data register and alternately reading said data from said first data register and said second data register,
- wherein each of said first memory and said second memory is not concurrently written and read.
Circuitry for providing an efficient FIFO memory comprising:
- means for receiving data having a plurality of portions;
- means for alternately writing said data to a first memory means and a second memory means;
- and
- means for alternately reading said data from said first memory means and said second memory means, wherein means for alternately reading said data comprises means for alternately writing said data to a first data register means and a second data register means and means for alternately reading said data from said first data register means and said second data register means,
- wherein each of said first memory means and said second memory means is not concurrently written and read.
FIFO memory comprising:
- a first memory bank and a second memory bank;
- a first data register and a second data register;
- WRITE logic operative to receive data having a plurality of portions and to alternately write said data to said first memory bank and said second memory bank;
- and
- READ logic operative to alternately read said data from said first memory bank and said second memory bank, wherein the READ logic is further operative to alternately write said data to said first data register and said second data register and alternately read said data from said first data register and said second data register,
- wherein each of said first memory bank and said second memory bank is not concurrently written and read.
A method of providing an efficient FIFO memory comprising:
- receiving data having a plurality of portions;
- alternately writing said data to a first memory and to a second memory, wherein at least two consecutive portions of data are written to one of said first memory and said second memory;
- and
- alternately reading said data from said first memory and said second memory,
- wherein each of said first memory and said second memory is not concurrently written and read.
Circuitry for providing an efficient FIFO memory comprising:
- means for receiving data having a plurality of portions;
- means for alternately writing said data to a first memory means and to a second memory means, wherein at least two consecutive portions of data are written to one of said first memory means and said second memory means;
- and
- means for alternately reading said data from said first memory means and said second memory means,
- wherein each of said first memory means and said second memory means is not concurrently written and read.
FIFO memory comprising:
- a first memory bank and a second memory bank;
- WRITE logic operative to receive data having a plurality of portions and to alternately write said data to said first memory bank and to said second memory bank, wherein at least two consecutive portions of data are written to one of said first memory bank and said second memory bank;
- and
- READ logical operative to alternately read said data from said first memory bank and said second memory bank,
- wherein each of said first memory bank and said second memory bank is not concurrently written and read.
Dependencies are inferred from the claim text.