Method and system to compensate for scanner system timing variability in a semiconductor wafer fabrication system
AssigneeASML Holding N.V.
InventorHilario L. Oh
Life of this patent
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Abstract
A semiconductor wafer fabrication system that includes at least a track system and a scanner system compensates for deviations from nominal periodicity in the scanner system by dynamically introducing time delays when such deviations are detected. Preferably prior art static wait states are also introduced into the wafer recipe to reduce probability of resource conflicts. The resultant semiconductor wafer fabrication system can enjoy enhanced wafer throughput in that synchronization of wafer flow is maintained, despite such deviations.
Claims20
In a semiconductor wafer fabrication system that includes at least a track system and a scanner system, a method of compensating the fabrication system for deviations from nominal scanner system clock periodicity, the method comprising the following steps:
- (a) operating said scanner system responsive to a signal from a scanner system dock;
- (b) operating said track system responsive to a signal from a track system clock;
- (c) pre-determining and inserting pre-planned wait states as needed to avoid conflict for resources in said semiconductor wafer fabrication system prior to operating said semiconductor wafer fabrication system;
- and
- (d) determining deviation from nominal timing in said scanner clock and dynamically inserting time delay as needed in said semiconductor wafer fabrication system to compensate for such deviation.
A semiconductor wafer fabrication system comprising:
- a scanner system operating responsive to a signal from a scanner system clock;
- a track system operating responsive to a signal from a track system clock;
- means for moving at least one wafer within said semiconductor wafer fabrication system;
- means for inserting pre-planned wait states in said single-clock semiconductor wafer fabrication system to reduce conflict for resources in said semiconductor wafer fabrication system;
- and
- means for dynamically inserting time delay as needed in said semiconductor wafer fabrication system to compensate for disturbance in periodicity of said scanner clock.
For use in operating a semiconductor wafer fabrication system that includes at least a scanner system operating responsive to a signal from a scanner system clock, and a track system operating responsive to a signal from a track system clock, a computer readable medium storing a computer program that when executed carries out at least one of the following steps:
- (a) pre-determining and inserting pre-planned wait states as needed to avoid conflict for resources in said semiconductor wafer fabrication system prior to operating said semiconductor wafer fabrication system;
- (b) determining deviations from nominal periodicity in said scanner system clock;
- and
- (c) calcu1ating and dynamically inserting time delay as needed in said semiconductor wafer fabrication system to compensate for said deviations.
Dependencies are inferred from the claim text.