Programmable logic device with time-multiplexed interconnect
AssigneeXilinx, Inc.
InventorStephen M. Trimberger
Life of this patent
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Abstract
A PLD includes at least one portion of the programmable interconnect that can be time multiplexed. The time multiplexed interconnect allows signals to be routed on shared interconnect at different times to different destinations, thereby increasing the functionality of the PLD. Multiple sources can use the same interconnect at different times to send signals to their respective destinations. To ensure proper sharing of the interconnect, the sources can include selection devices (such as multiplexers), and the destinations can include capture devices (such as flip-flops), wherein the selection devices and the capture devices are controlled by the same time multiplexing signal. To optimize the time multiplexing interconnect, as much of the same interconnect is shared as possible.
Claims20
A method of propagating signals on programmable interconnect in a programmable logic device, the method comprising:
- selecting by a selection device between source signals to drive a shared programmable interconnect portion located on the programmable logic device;
- and
- coordinating latching of the source signals in corresponding capture devices via a time multiplexing signal generator coupled to the selection device and the capture devices;
- and
- providing one of the source signals from the time multiplexing signal generator to one or more flip flops without a clock delay.
A method of propagating signals in a programmable logic device, the method comprising:
- selecting by a selection device between source signals to route signals onto a shared programmable interconnect on the programmable logic device;
- routing signals from the shared programmable interconnect to the capture devices through a first programmable interconnect point;
- and
- controlling by a clock applied to the selection device and capture devices the provision of the source signals through the selection device to the capture devices, wherein a first one of the signals is latched to a first one of the capture devices during a first phase of the time multiplexing signal and a second one of the signals is latched to a second one of the capture devices during a second phase of the time multiplexing signal.
A configured programmable logic device comprising:
- a multiplexer which chooses between source signals to drive a shared programmable interconnect on the programmable logic device;
- flip flops which receive the source signals from the shared programmable interconnect;
- and
- a clock which is coupled to the multiplexer and flip flops and provides one of the source signals from the multiplexer to one or more of the flip flops without a clock delay.
Dependencies are inferred from the claim text.