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US 7,138,823 B2Granted
Apparatus and method for independent control of on-die termination for output buffers of a memory device
AssigneeMicron Technology, Inc.
InventorsJeff Janzen, Wen Li
Life of this patent
Estimating the term…
Abstract
An apparatus and method providing independent control of on-die termination (ODT) of output buffers. The ODTs for the buffer circuits of an input/output (I/O) buffer can be enabled and disabled in response to an ODT control signal. Additionally, the ODTs for a first set of the buffer circuits can be enabled and disabled responsive to the ODT control signal and the ODT for at least one of a second set of the buffer circuits is disabled.
Claims46
An output buffer, comprising:
- a plurality of buffer circuits, each buffer circuit having an input circuit and an output circuit, and further having an on-die termination (ODT) circuit coupled to the input and output circuits, the ODT circuit having an activation node to which an ODT activation signal is coupled to enable and disable the ODT circuit;
- and
- an ODT control circuit coupled to the plurality of buffer circuits and having an ODT mode select node to which an ODT mode select signal is applied and an ODT control node to which an ODT control signal is applied, in response to a first state of the ODT mode select signal and an active ODT control signal, the ODT control circuit configured to generate an active ODT activation signal for the plurality of buffer circuits, and in response to a second state of the ODT mode select signal and an active ODT control signal, the ODT control circuit configured to generate an active ODT activation signal for a first set of the plurality of buffer circuits and an inactive ODT signal for a second set of the plurality of buffers circuit.
An output buffer, comprising:
- at least one data strobe buffer circuit having an data strobe node at which a read strobe signal is provided and a write strobe signal is received;
- a plurality of data buffer circuits, each having a data output node at which a read data signal is provided and a write data signal is received;
- and
- a resistive termination circuit having resistive terminations coupled to the data strobe node and the output nodes and further having a strobe termination activation node at which a first control signal is applied and an I/O termination activation node at which a second control signal is applied, the resistive termination circuit configured to enable the resistive terminations coupled to the data strobe node in response to the first control signal and enable the resistive terminations coupled to the data output nodes in response to the second control signal.
1 more element
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- and
- an output buffer coupled to the data bus and the control circuit, the output buffer comprising:
- a plurality of buffer circuits, each buffer circuit having an input circuit and an output circuit, and further having an on-die termination (ODT) circuit coupled to the input and output circuits, the ODT circuit having an activation node to which an ODT activation signal is coupled to enable and disable the ODT circuit;
- and
- an ODT control circuit coupled to the plurality of buffer circuits and having an ODT mode select node to which an ODT mode select signal is applied and an ODT control node to which an ODT control signal is applied, in response to a first state of the ODT mode select signal and an active ODT control signal, the ODT control circuit configured to generate an active ODT activation signal for the plurality of buffer circuits, and in response to a second state of the ODT mode select signal and an active ODT control signal, the ODT control circuit configured to generate an active ODT activation signal for a first set of the plurality of buffer circuits and an inactive ODT signal for a second set of the plurality of buffers circuit.
9 more elements
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- and
- an output buffer coupled to the data bus and the control circuit, the output buffer comprising:
- at least one data strobe buffer circuit having an data strobe node at which a read strobe signal is provided and a write strobe signal is received;
- a plurality of data buffer circuits, each having a data output node at which a read data signal is provided and a write data signal is received;
- and
- a resistive termination circuit having resistive terminations coupled to the data strobe node and the output nodes and further having a strobe termination activation node at which a first control signal is applied and an output termination activation node at which a second control signal is applied, the resistive termination circuit configured to enable the resistive terminations coupled to the data strobe node in response to the first control signal and enable the resistive terminations coupled to the output nodes in response to the second control signal.
10 more elements
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- an output buffer coupled to the data bus and the control circuit, the output buffer comprising:
- a plurality of output buffer circuits, each buffer circuit having an input circuit and an output circuit, and further having an on-die termination (ODT) circuit coupled to the input and output circuits, the ODT circuit having an activation node to which an ODT activation signal is coupled to enable and disable the ODT circuit;
- and
- an ODT control circuit coupled to the plurality of buffer circuits and having an ODT mode select node to which an ODT mode select signal is applied and an ODT control node to which an ODT control signal is applied, in response to a first state of the ODT mode select signal and an active ODT control signal, the ODT control circuit configured to generate an active ODT activation signal for the plurality of buffer circuits, and in response to a second state of the ODT mode select signal and an active ODT control signal, the ODT control circuit configured to generate an active ODT activation signal for a first set of the plurality of buffer circuits and an inactive ODT signal for a second set of the plurality of buffers circuit.
13 more elements
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- an output buffer coupled to the data bus and the control circuit, the I/O buffer comprising:
- at least one data strobe buffer circuit having an data strobe node at which a read strobe signal is provided and a write strobe signal is received;
- a plurality of data buffer circuits, each having a data output node at which a read data signal is provided and a write data signal is received;
- and
- a resistive termination circuit having resistive terminations coupled to the data strobe node and the data output nodes and further having a strobe termination activation node at which a first control signal is applied and an output termination activation node at which a second control signal is applied, the resistive termination circuit configured to enable the resistive terminations coupled to the data strobe node in response to the first control signal and enable the resistive terminations coupled to the data output nodes in response to the second control signal.
14 more elements
A method of configuring on-die terminations (ODTs) for a plurality of output buffer circuits, comprising:
- in a first mode, enabling and disabling the ODTs for the plurality of output buffer circuits in response to an ODT control signal;
- and
- in a second mode, disabling at least one ODT for a first set of the plurality of output buffer circuits and enabling and disabling the ODTs for a second set of the plurality of output buffer circuits in response to the ODT control signal.
A method of controlling termination circuits of data strobe and data buffer circuits, comprising:
- enabling and disabling the termination circuit of the data strobe buffer circuit in response to a set of control signals;
- and
- enabling and disabling the termination circuits of at least one of the data buffer circuits in response to the set of control signals, the termination circuit of the data strobe buffer circuit not responding identically as the termination circuits of the data buffer circuits in response to the set of control signals.
Dependencies are inferred from the claim text.