Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure

A layout structure of a semiconductor integrated circuit, comprising:

• a channel-less type standard cell array formed by arranging one or more of each of a plurality of types of standard cells having respective logical functions in rows and columns, an outer perimeter of the standard cell array having vertical and horizontal sides;
• first proximity dummy bands formed by arranging a plurality of first proximity dummy cells along each of at least some of the vertical sides of the standard cell array;
• and
• second proximity dummy bands formed by arranging a plurality of second proximity dummy cells along each of at least some of the horizontal sides of the standard cell array;
• wherein:
• each of the plurality of types of standard cells includes standard cell patterns in a plurality of layers arranged in a standard cell frame having an upper, a lower, a left, and a right side, the plurality of types of standard cells have a common height defined by distances between the upper and the lower sides of the standard cell frames;
• each of the vertical and horizontal sides of the standard cell array is formed with the sides of the frames of the standard cells arranged in an outer-most portion of the standard cell array;
• each of the first proximity dummy cells includes a first proximity dummy pattern, which does not contribute to a logical function of the semiconductor integrated circuit, in at least one of the plurality of layers arranged in a first proximity dummy cell frame having an upper, a lower, a left, and a right side, each of the first proximity dummy cells has a height defined by a distance between the upper and the lower sides of the first proximity dummy cell frame of k1 times the common height of the standard cells, where k1 is an integer not less than one;
• each of the second proximity dummy cells includes a second proximity dummy pattern, which does not contribute to the logical function of the semiconductor integrated circuit, in the at least one of the plurality of layers arranged in a second proximity dummy cell frame having an upper, a lower, a left, and a right side;
• each of the first proximity dummy bands is formed such that the upper and the lower sides of the frames of the plurality of first proximity dummy cells are in contact with each other and such that one of the left and right sides of the frame of each of the plurality of first proximity dummy cells is in contact with a corresponding portion of the vertical sides of the standard cell array;
• and
• each of the second proximity dummy bands is formed such that one of the upper and the lower sides of the frame of each of the plurality of second proximity dummy cells is in contact with a corresponding portion of the horizontal sides of the standard cell array.

A photomask comprising a mask pattern for forming one of a plurality of layers in a layout structure of a semiconductor integrated circuit by producing a reduced image of the mask pattern on a semiconductor substrate using an exposing light having a wavelength of λ, the layout structure comprising:

• a channel-less type standard cell array formed by arranging one or more of each of a plurality of types of standard cells having respective logical functions in rows and columns, an outer perimeter of the standard cell array having vertical and horizontal sides;
• first proximity dummy bands formed by arranging a plurality of first proximity dummy cells along each of at least some of the vertical sides of the standard cell array;
• and
• second proximity dummy bands formed by arranging a plurality of second proximity dummy cells along each of at least some of the horizontal sides of the standard cell array;
• wherein:
• each of the plurality of types of standard cells includes standard cell patterns in the plurality of layers arranged in a standard cell frame having an upper, a lower, a left, and a right side, the plurality of types of standard cells have a common height defined by distances between the upper and the lower sides of the standard cell frames;
• each of the vertical and horizontal sides of the standard cell array is formed with the sides of the frames of the standard cells arranged in an outer-most portion of the standard cell array;
• each of the first proximity dummy cells includes a first proximity dummy pattern, which does not contribute to a logical function of the semiconductor integrated circuit, in at least one of the plurality of layers arranged in a first proximity dummy cell frame having an upper, a lower, a left, and a right side, each of the first proximity dummy cells has a height defined by a distance between the upper and lower sides of the first proximity dummy cell frame of k1 times the common height of the standard cells, where k1 is an integer not less than one;
• each of the second proximity dummy cells includes a second proximity dummy pattern, which does not contribute to the logical function of the semiconductor integrated circuit, in the at least one of the plurality of layers arranged in a second proximity dummy cell frame having an upper, a lower, a left, and a right side;
• each of the first proximity dummy bands is formed such that the upper and the lower sides of the frames of the plurality of first proximity dummy cells are in contact with each other and such that one of the left and the right sides of the frame of each of the plurality of first proximity dummy cells is in contact with a corresponding portion of the vertical sides of the standard cell array;
• and
• each of the second proximity dummy bands is formed such that one of the upper and the lower sides of the frame of each of the plurality of second proximity dummy cells is in contact with a corresponding portion of the horizontal sides of the standard cell array.