Decimal multiplication using digit recoding
AssigneeInternational Business Machines Corporation
InventorsSteven R. Carlough, Eric M. Schwarz
Life of this patent
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Abstract
A system and methodology for decimal multiplication in a microprocessor comprising: a recoder configured to recode decimal digits of a first operand to a corresponding set of {−5 to +5}. The recoder also configured to recode decimal digits of a second operand to a corresponding set of {−5 to +5}. The system also includes a multiplier array of digit multipliers, each digit multiplier configured to generate a partial product of a selected digit of a recoded first operand and a recoded second operand; and an adder array of digit adders, each adder configured to generate a sum of the partial products, wherein a least significant digit of the sum is shifted to a results register, and each adder includes carry feedback.
Claims29
A system for decimal multiplication in a microprocessor comprising:
- a recoder configured to recode decimal digits of a first operand to a corresponding set of {−5 to +5} and configured to recode decimal digits of a second operand to a corresponding set of {−5 to +5};
- a multiplier array of digit multipliers, each digit multiplier configured to generate a partial product of a selected digit of a recoded first operand and a recoded second operand;
- and
- an adder array of digit adders, each adder configured to generate a sum of said partial products, wherein a least significant digit of said sum is shifted to a results register, and each adder includes carry feedback.
A method for decimal multiplication comprising:
- recoding decimal digits of a first operand to a corresponding set of {−5 to +5};
- recoding decimal digits of a second operand to a corresponding set of {−5 to +5};
- generating a partial product of a selected digit of a recoded first operand and a recoded second operand with a multiplier array of digit multipliers;
- and
- accumulating a sum of said partial products with an adder array of digit adders, wherein a least significant digit of said sum is shifted to a results register, and each adder including carry feedback.
A system for decimal multiplication in a microprocessor comprising:
- a means for recoding decimal digits of a first operand to a corresponding set of {−5 to +5};
- a means for recoding decimal digits of a second operand to a corresponding set of {−5 to +5};
- a means for generating a partial product of a selected digit of a recoded first operand and a recoded second operand with a multiplier array of digit multipliers;
- and
- a means for accumulating a sum of said partial products with an adder array of digit adders, wherein a least significant digit of said sum is shifted to a results register, and each adder including carry feedback.
Dependencies are inferred from the claim text.