Hyper-ring oscillator

A ring oscillator, comprising:

• a first logic circuit forming a first loop having a first odd number of inverting stages and a first input element;
• a second logic circuit forming a second loop having an input element other than the first input element, such that phase interpolation occurs at a first node common to the first and second loops to produce a first oscillation signal;
• and
• a third logic circuit forming a third loop having a second odd number of inverting stages, such that the phase interpolation occurs at a second node, the second node being common to the second and third loops to produce a second oscillation signal having a frequency higher than the first oscillation signal.

A ring oscillator, comprising:

• first, second and third circuit loops, wherein each loop has a different input element from the other loops;
• and
• a node common to the first and second circuit loops at which phase interpolation occurs, producing a first oscillating signal having a frequency higher than an oscillating signal provided by the first loop independently;
• and
• a second node at which phase interpolation occurs, the oscillator producing an oscillating signal having a frequency higher than the first oscillating signal.

A ring oscillator comprising:

• a first node located at a common output of first and second circuit loops, wherein the first and second loops have different input elements, phase interpolation to occur at the first node to produce a first oscillation signal;
• a third circuit loop arranged such that a second node is common to the second and third circuit loops and at which phase interpolation occurs to produce a second oscillation signal having a frequency higher than the first oscillation signal, the second node located one inverting stage prior to the first node;
• a third node located one inverting stage after the first node;
• and
• a fourth node, located so as to be common to at least two circuit loops and such that phase interpolation occurs at the fourth node.

A method comprising:

• producing a first output signal having a first phase at a first node from a first circuit loop having a first input element;
• producing a second output signal having a second phase at the first node from a second circuit loop having an input element other than the first input element;
• producing a third output signal having a third phase at a second node;
• interpolating the first and second phases at the first node to produce a first resulting output signal having an output frequency higher than a frequency of the first output signals;
• and
• interpolating the third output signal with at least one of the first and second output signals at the second node, causing a second resulting output signal to have a frequency higher than the first resulting output signal.

A system comprising:

• a memory controller generating a plurality of command and address signals;
• a memory module comprising a plurality of memory devices and receiving the plurality of command and address signals from the memory controller;
• each of the memory devices to store data comprising;
• a plurality of memory cells to store the data;
• a ring oscillator operating for a phase locked loop, the ring oscillator comprising;
• a first logic circuit forming a first loop having a first input element;
• and
• a second logic circuit forming a second loop having a different input element than the first input element, such that phase interpolation occurs at a node common to the first and second loops to produce a first oscillation signal;
• and
• a third logic circuit forming a third loop to produce a third output signal having a third phase at a second node such that phase interpolation occurs at the second node to produce a second output signal having a frequency higher than the first resulting output signal.

A system comprising:

• a memory controller generating a plurality of command and address signals and receiving a first clock signal;
• a memory module comprising a plurality of memory devices and receiving the plurality of command and address signals from the memory controller;
• a clock generator generating the first clock signal and transferring the first clock signal to the memory controller, the clock generator comprising a clock source and a phase locked loop including a ring oscillator;
• the ring oscillator comprising:
• a first logic circuit forming a first loop having a first input element;
• a second logic circuit forming a second loop having a different input element than the first input element, such that phase interpolation occurs at a node common to the first and second loops producing a first output signal;
• a third logic circuit forming a third loop producing a third output signal having a third phase at a second node;
• and
• interpolating the third output signal with at least one of the first and second output signals at the second node, causing a second output signal to have a freciuency higher than the first output signal.