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US 7,132,861 B1Granted
Amplifier with digital DC offset cancellation feature
AssigneeApplied MicroCircuits Corporation
InventorsWei Fu, Joseph James Balardeta
Life of this patent
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Abstract
A high speed, high sensitivity post amplifier as described herein includes a digitally-controlled DC offset cancellation feature. The amplifier circuit is configured to provide DC offset voltage levels in response to a digital control signal, where the digital control signal is generated based upon a data error metric such as bit error rate. The AC signal path and the DC offset adjustment signal path in the amplifier circuit are separated to facilitate operation with normal power supply voltages, and to achieve low power operation.
Claims8
An amplifier circuit comprising:
- a first transistor having a positive input signal node and a first current input node;
- a second transistor having a negative input signal node and a second current input node;
- a positive output node connected to said second current input node;
- a negative output node connected to said first current input node;
- a matching impedance connected between said positive input signal node of said first transistor and said negative input signal node of said second transistor;
- a third transistor for generating a positive component of a DC offset cancellation voltage, said third transistor having a control signal node and a third current input node connected to said positive output node;
- a fourth transistor for generating a negative component of said DC offset cancellation voltage, said fourth transistor having a control signal node and a fourth current input node connected to said negative output node;
- and
- a digitally-controlled bias current architecture connected to said control signal node of said third transistor and to said control signal node of said fourth transistor, said bias current architecture being configured to adjust said positive component of said DC offset cancellation voltage and said negative component of said DC offset cancellation voltage;
- wherein said bias current architecture comprises:
- a fifth transistor having a fifth current input node connected to said control signal node of said third transistor and a first bias signal node for a first DC offset control signal;
- a sixth transistor having a sixth current input node connected to said control signal node of said fourth transistor and a second bias signal node for a second DC offset control signal;
- a first resistance having a first end connected to said control signal node of said third transistor and a second end connected to a supply voltage;
- and
- a second resistance having a first end connected to said control signal node of said fourth transistor and a second end connected to said supply voltage.
12 more elements
Dependencies are inferred from the claim text.