Method for selectively disabling interrupts on a secure execution mode-capable processor
AssigneeAdvanced Micro Devices, Inc.
InventorsDavid S. Christie, Geoffrey S. Strongin, Kevin J. McGrath
Life of this patent
Estimating the term…
Abstract
A method of controlling a secure execution mode-capable processor includes allowing a plurality of interrupts to interrupt the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a non-secure execution mode. The method also includes disabling the plurality of interrupts from interrupting the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a secure execution mode.
Claims26
A method of controlling a secure execution mode-capable processor, said method comprising:
- operating in a non-secure execution mode;
- entering a secure execution mode by initializing, from the non-secure execution mode, and executing a trusted secure operating system code segment that has been verified external to said secure execution mode-capable processor;
- allowing a plurality of interrupts to interrupt said secure execution mode-capable processor when said secure execution mode-capable processor is operating in a non-secure execution mode;
- and
- disabling said plurality of interrupts, including software interrupts, from interrupting said secure execution mode-capable processor and ensuring that said plurality of interrupts cannot be re-enabled, except by said trusted secure operating system code segment when said secure execution mode-capable processor is operating in said secure execution mode.
A secure execution mode-capable processor comprising:
- execution logic configured to execute program instructions in a non-secure execution mode;
- wherein the execution logic is further configured to execute program instructions in a secure execution mode in response to a secure execution mode initialization sequence initiated from the non-secure execution mode, wherein said program instructions include a trusted secure operating system code segment that has been verified external to said secure execution mode-capable processor;
- and
- interrupt control logic coupled to said execution logic and configured to allow a plurality of interrupts to interrupt said execution logic during operation in a non-secure execution mode;
- wherein said interrupt control logic is further configured to disable said plurality of interrupts, including software interrupts, from interrupting said execution logic and to ensure that said plurality of interrupts cannot be re-enabled, except by said trusted secure operating system code segment, during operation in said secure execution mode.
A secure execution mode-capable processor comprising:
- execution logic configured to execute program instructions in a non-secure execution mode;
- wherein the execution logic is further configured to execute program instructions in a secure execution mode in response to a secure execution mode initialization sequence initiated from the non-secure execution mode, wherein said program instructions include a trusted secure operating system code segment that has been verified external to said secure execution mode-capable processor;
- means for allowing a plurality of interrupts to interrupt said secure execution mode-capable processor when said secure execution mode-capable processor is operating in a non-secure execution mode;
- and
- means for disabling said plurality of interrupts, including software interrupts, from interrupting said secure execution mode-capable processor and to ensure that said plurality of interrupts cannot be re-enabled, except by said trusted secure operating system code segment, when said secure execution mode-capable processor is operating in said secure execution mode.
Dependencies are inferred from the claim text.