Method and structure to improve reliability of copper interconnects
AssigneeASM Nutool, Inc.
InventorsBulent M. Basol, Homayoun Talieh
Life of this patent
Estimating the term…
Abstract
A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.
Claims21
A method of forming a conductor structure on a surface of a wafer, the surface including cavities separated by field regions, the method comprising:
- depositing a seed layer with a substantially uniform thickness on the field regions and in the cavities of the surface having a barrier layer thereon, wherein the barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity;
- forming a conductive layer by electrodepositing a conductive material on the seed layer, wherein the conductive material fills the remaining volume of each cavity and wherein a thickness of the conductive layer over the field regions is between about 100 nm and about 200 nm;
- and
- annealing the wafer to increase grains size in the conductive layer and the seed layer.
A method of forming a conductor structure on a surface of a wafer, the surface including cavities separated by field regions, the method comprising:
- depositing a seed layer with a substantially uniform thickness on the field regions and in the cavities of the surface having a barrier layer thereon, wherein the barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity;
- forming a substantially planar conductive layer by depositing a conductive material on the seed layer, wherein the conductive material fills the remaining volume of each cavity and wherein a thickness of the conductive layer over the field regions is between about 100 nm and about 200 nm and is about 2 to 20 times the thickness of the seed layer thickness;
- and
- annealing the wafer to form large grains in the conductive layer and the seed layer.
Dependencies are inferred from the claim text.