US 7,127,697 B1 · Methods of utilizing programmable logic devices having localized defects in application-specific products

Abstract

Methods of utilizing partially defective PLDs, i.e., PLDs having localized defects. A partially defective PLD is tested for compatibility with a particular configuration bitstream. If the partially defective PLD is compatible with the bitstream (i.e., if the localized defect has no effect on the functionality of the design implemented by the bitstream), a product is made available that includes both the bitstream and the partially defective PLD. In some embodiments, the bitstream is stored in a memory device such as a programmable read-only memory (PROM). In some embodiments, the product is a chip set that includes the partially defective PLD and a separately-packaged PROM in which the bitstream has previously been stored. In some embodiments, the PROM is manufactured as part of the FPGA die.

Claims14

Dependent claims

A method of utilizing a partially defective programmable logic device (PLD), the method comprising:

testing for compatibility between the partially defective PLD and a configuration bitstream,
the testing for compatibility, comprising verifying functionality of a design using a design specific test on the partially defective PLD having the configuration bitstream;
and
marking the partially defective PLD with an identifier identifying the configuration bitstream as usable with the partially defective PLD if the partially defective PLD and the configuration bitstream are determined to be compatible.

1 more element

Dependencies are inferred from the claim text.

Methods of utilizing programmable logic devices having localized defects in application-specific products

Life of this patent

Methods of utilizing programmable logic devices having localized defects in application-specific products

Life of this patent

Abstract

Claims14