Timing based scan chain implementation in an IC design

For use with a timing database, a computer implemented process for electronic design automation comprising:

• receiving a netlist including at least one first scan cell triggered by a first clock triggering edge and at least one second scan cells triggered by a second clock triggering edge;
• receiving from the timing database clock timing information that indicates instance clock trigger time (CTT) of the first clock triggering edge at each of the at least one first start cell and that indicates instance CTT of the second clock triggering edge at each of the at least one second scan cell;
• and
• ordering each at least one first scan cell and each at least one second scan cell relative to each other in a design in descending order of instance CTTs.

For use with a timing database, a computer implemented process for electronic design automation comprising:

• receiving a netlist including multiple scan cells in which a first set of the multiple scan cells is triggered by a first triggering clock edge and a second set of the multiple scan cells is triggered by a second triggering clock edge;
• receiving from the timing database clock timing information that indicates a source clock trigger time (CTT) of the first clock triggering edge and that indicates a source CTT of the second clock triggering edge;
• receiving from the timing database clock timing information that respectively indicates instance CTTs of the first triggering clock edge at respective scan cells of the first set and that respectively indicates instance CTTs of the second triggering dock edge at respective scan cells of the second set;
• and
• ordering the multiple scan cells in a design so that the scan cells are ordered relative to each other in descending order of source CTTs and so that scan cells are further ordered relative to each other in descending order of arrival time of their instance CTTs.