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US 7,127,692 B2Granted
Timing abstraction and partitioning strategy
AssigneeLSI Logic Corporation
InventorChristopher L. Hamlin
Life of this patent
Estimating the term…
Abstract
The present invention is directed to a timing abstraction and partitioning strategy for integrated circuit design. A method for designing an integrated circuit may include monitoring user interaction with logical blocks during a function design process of an integrated circuit. Indications of timing properties are derived during the functional design process.
Claims2
A method of designing an integrated circuit, comprising:
- monitoring user interaction with logical blocks during a functional design process of an integrated circuit;
- and
- deriving, without affecting the functional design process, indications of timing properties during the functional design process based on the monitored user interaction, the indications of timing properties including background heuristics describing timing properties of the logical blocks within a hierarchy of functional elements of the integrated circuit,
- wherein the indications of timing properties are used during back end stages to complete timing closure and verification after completion of the functional design process, and
- wherein a mathematical formulation is provided based on the achieved functional design and the derived timing indications, the mathematical formulation including functional description of the integrated circuit, block structure in which a relationship of logical blocks is expressed, hierarchy in which the logical blocks are expressed, timing implications of logical blocks in terms of timing specification for the integrated circuit, content of timing indications and structure of timing indications.
2 more elements
A system for designing an integrated circuit, comprising:
- a memory suitable for storing a program of instructions;
- and
- a processor communicatively coupled to the memory, the processor suitable for performing the program of instructions, wherein the program of instructions configures the processor to
- monitor user interaction with logical blocks during a functional design process of an integrated circuit;
- and
- derive, without affecting the functional design process, indications of timing properties during the functional design process based on the monitored user interaction, the indications of timing properties including background heuristics describing timing properties of the logical blocks within a hierarchy of functional elements of the integrated circuit,
- wherein the indications of timing properties are used during back end states to complete timing closure and verification after completion of the functional design process, and
- wherein a mathematical formulation is provided based on the achieved functional design and the derived timing indications, the mathematical formulation including functional description of the integrated circuit block structure in which a relationship of logical blocks is expressed, hierarchy in which the logical blocks are expressed, timing implications of logical blocks in terms of timing specification for the integrated circuit, content of dining indications and structure of timing indications.
5 more elements
Dependencies are inferred from the claim text.