Method for preventing circuit failures due to gate oxide leakage
AssigneeInternational Business Machines Corporation
InventorsPaul D. Kartschoke, Thomas G. Mitchell, Norman J. Rohrer, Ronald D. Rose
Life of this patent
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Abstract
A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source for a static noise analysis of the circuit.
Claims20
A method for identifying and preventing logic errors in an integrated circuit caused by gate oxide leakage, comprising:
- locating and compiling every net, which is an interconnect between a driving circuit and a receiving circuit, in an integrated circuit;
- determining, for each receiving circuit, the gate length of each current sink transistor device;
- determining, for each receiving circuit, the entire current source to current sink resistive interconnect network;
- determining, for each driving circuit, the weakest pullup circuit and the weakest pulldown circuit and converting them to equivalent resistances;
- defining and modeling, for each net, a comprehensive DC resistance network of the driving circuit resistance, the interconnect resistance, and the current source resistance;
- determining, for each sink transistor gate, the net pulled up and net pulled down to determine a DC solution of the gate voltage offset at each sink transistor gate;
- determining any failing gates with a reference level voltage check of the gate voltage offset relative to a given threshold;
- using a static noise analysis tool to combine the determined gate voltage offset as a noise source with other noise sources, and performing a sensitivity analysis to determine the effect of the noise on the function on each receiving circuit gate;
- redesigning each failed net.
A method for identifying and preventing logic errors in an integrated circuit caused by gate oxide leakage, comprising:
- defining every net, which is an interconnect between a driving circuit and a receiving circuit, in an integrated circuit;
- determining, for each receiving circuit, the gate length of each current sink transistor device;
- determining, for each receiving circuit, the entire current source to current sink resistive interconnect network;
- determining, for each driving circuit, the weakest pullup circuit and the weakest pulldown circuit and converting them to equivalent resistances;
- defining a model, for each net, of a comprehensive DC resistance network of the driving circuit resistance, the interconnect resistance, and the current source resistance;
- determining, for each sink transistor gate, the net pulled up and net pulled down to determine a DC solution of the gate voltage offset at each sink transistor gate;
- determining any failing gates with a reference level voltage check of the gate voltage offset relative to a given threshold;
- combining the determined gate voltage offset as a noise source with other noise sources while performing a sensitivity analysis to determine the effect of the noise on the function on each receiving circuit gate;
- redesigning each failed net.
Dependencies are inferred from the claim text.