ACS circuit and viterbi decoder with the circuit

A Viterbi decoder for decoding a string of encoded data using partial response maximum likelihood with run-length code constraint in a DVD storage system, a trellis structure in the Viterbi decoder containing N trellis states with two-branches and K trellis states with only one branch responsive to the run-length code constraint, wherein N and K are positive integers, the Viterbi decoder comprising:

• a branch metric generator for calculating and outputting branch metrics for each branch responsive to encoded data;
• an add-compare-select unit for receiving the branch metrics and (N+K) previous candidate state metrics respective to the trellis state in the trellis structure and outputting N comparison signals;
• and
• a survivor path memory and decoding unit for receiving the N comparison signals and generating a string of decoded data;
• wherein the add-compare-select unit comprises:
• (2N +K) registers for storing the (N+K) previous candidate state metrics respective to the trellis state, wherein N previous candidate state metrics are stored in duplicate registers;
• N add-compare-select processors for receiving values stored in the 2N first registers and corresponding branch metrics, and outputting N first candidate state metrics, N second candidate state metrics and the N comparison signals, the N first candidate state metrics and the N second candidate state metrics being stored in the registers;
• and
• K first adders for respectively adding a corresponding previous candidate state metric and a branch metric to generate a candidate state metric, which is stored in the register;
• wherein each add-compare-select processor comprises:
• a second adder for adding a first value stored in one of the registers and a first branch metric to generate a first addition result;
• a third adder for adding a second value stored in another of the registers and the first branch metric to generate a second addition result;
• a fourth adder for adding the first value and a second branch metric to generate a third addition result;
• a fifth adder for adding the second value and the second branch metric to generate a fourth addition result;
• a comparator for comparing the first value and the second value, and outputting a comparison signal indicating which one is minimum;
• a first selector for selecting either the first addition result or the second addition result as the first candidate state metric according to the comparison signal;
• and
• a second selector for selecting either the third addition result or the fourth addition result as the second candidate state metric according to the comparison signal;
• wherein each add-compare-select processor is configured with the registers being located before the comparator.

A decoding method of a Viterbi decoder for decoding a string of encoded data using partial response maximum likelihood with run-length code constraint in a DVD storage system, a trellis structure in the Viterbi decoder containing N trellis states with two-branches and K trellis states with only one branch responsive to the run-length code constraint, wherein N and K are positive integers, the Viterbi decoder having a branch metric generator, an add-compare-select unit, and a survivor path memory and decoding unit, the add-compare-select unit having (2N+K) registers, N add-compare-select processors and K adders, the method comprising the steps of:

• calculating and outputting branch metrics for each branch responsive to encoded data by the branch metric generator;
• respectively adding 2N previous candidate state metrics respective to a trellis state in the trellis structure and a first branch metric from the trellis state to generate N first addition results and N second addition results, and simultaneously comparing the 2N previous candidate state metrics, and then outputting N comparison signals by the add-compare-select processor;
• selecting N candidate state metrics from the N first addition results and the N second addition results according to the N comparison signals by the add-compare-select processor;
• and
• receiving the N comparison signals and generating a string of decoded data by survivor path memory and decoding unit;
• wherein each add-compare-select processor is configured to enable the adding step and the comparing step to be executed concurrently.

A decoding method of a Viterbi decoder for decoding a string of encoded data using partial response maximum likelihood with run-length code constraint in a DVD storage system, a trellis structure in the Viterbi decoder containing N trellis states with two-branches and K trellis states with only one branch responsive to the run-length code constraint, wherein N and K are positive integers, the Viterbi decoder having a branch metric generator, an add-compare-select unit, and a survivor path memory and decoding unit, the add-compare-select unit having (2N+K) registers, N add-compare-select processors and K adders, the method comprising the steps of:

• calculating and outputting branch metrics for each branch responsive to encoded data by the branch metric generator;
• respectively adding 2N previous candidate state metrics respective to a trellis state in the trellis structure and a first branch metric from the trellis state to generate N first addition results and N second addition results, adding the 2N previous candidate state metrics and a second branch metric from the trellis state to generate N third addition results and N fourth addition results, and simultaneously comparing 2N previous candidate state metrics, and then outputting N comparison signals by the add-compare-select processor;
• selecting N first candidate state metrics from the N first addition results and the N second addition results, and N second candidate state metrics from the N third addition results and the N fourth addition results according to the N comparison signals by the add-compare-select processor;
• and
• receiving the N comparison signals and generating a string of decoded data by survivor path memory and decoding unit;
• wherein each add-compare-select processor is configured to enable the adding step and the comparing step to be executed concurrently.