Reconfigurable architecture for decoding telecommunications signals

A reconfigurable architecture for decoding data communications signals transmitted according to one of a plurality of coding schemes, said coding schemes comprising convolutional and turbo codes, said architecture comprising:

• a symbol history means for receiving an input symbol derived from said transmitted signals to be decoded and for providing a buffered input symbol delayed by a predetermined period;
• a butterfly processor configured for receiving said input symbol and for generating intermediate decoded results and new path metrics from said input symbol and old path metrics;
• comparator means for receiving said new path metrics and determining a greatest path metric obtained during a calculation of a column of a decoding trellis by said butterfly processor;
• a traceback and interleaver processor for receiving said greatest path metric and said decoded results;
• a first bank of multiplexers arranged to receive said new path metrics and log outputs from a first LogLikelihood processor and to output one thereof as process metrics;
• said process metrics being supplied to each of said first LogLikelihood processor and a second LogLikelihood processor, said first LogLikelihood processor receiving said buffered input symbol, each of said LogLikelihood processors determining a log- likelihood value, said values being supplied together with outputs of said traceback and interleaver processor to a LogLikelihood ratio processor for providing a decoded output for said input symbol from said architecture;
• said process metrics being further supplied to a processing chain configured to provide said old path metrics to said butterfly processor, said processing chain comprising a forward trellis processor for ordering said process metrics into a path metrics store, a second bank of multiplexers for selecting path metrics from said store or said process metrics for supply to a normalising processor also input with said greatest path metric, and a reverse trellis processor for receiving an output of said normalising processor to order normalised path metrics to form said old path metrics;
• and
• a control arrangement coupled to each of said symbol history means, said butterfly processing means, said comparator means, said first bank of multiplexers, said first LogLikelihood processor means, said second LogLikelihood processor means, said traceback and interleaver processor, said LogLikelihood ratio processor, said forward trellis processor, said path metric stores, said second bank of multiplexers, said normalising processor and said reverse trellis processor, said control arrangement being operable to configure said architecture for one of convolutional or turbo decoding according to one of a forward trellis coding or a reverse trellis coding.

A decoder, comprising:

• a plurality of computation units, each of said computation units performing a single function;
• wherein
• in a first mode of operation, at least a first subset of said computation units are arranged to decode an input symbol at a first time according to a first decoding mode, and
• in a second mode of operation, at least a second subset of said computation units, which includes at least one computation unit that was in said first subset, are arranged to decode said input signal at a second time according to a second decoding mode.

A telecommunications decoder for decoding input symbols to provide output data, said decoding involving evaluation of a trellis for each said input symbol, said decoder comprising:

• means for evaluating said trellis in a first direction;
• means for evaluating said trellis in a second direction;
• and
• means for enabling operation of one of said processors according to a determined coding arrangement of said input symbols wherein said decoding is based on covolutional codes.