Turbo decoder control for use with a programmable interleaver, variable block length, and multiple code rates

A decoder for use in data control support high-speed MAP decoding, the decoder comprising:

• an address generator for generating an address;
• a first memory unit for storing systematic data samples of a turbo codeword;
• a second memory unit for storing parity data samples of a top code and a bottom code of the turbo codeword;
• a third memory unit for storing bit probability likelihood ratios of the systematic data samples;
• a fourth memory unit for storing a de-interleaver definition;
• and
• a multiplexer for selecting between an output of the address generator and the fourth memory unit,
• wherein the address is simultaneously provided to at least the second memory unit and the fourth memory unit and an output of the multiplexer provides an address to the first memory unit and the third memory unit.

A decoder for use in data control supporting high-speed MAP decoding, the turbo decoder comprising:

• an address generator for generating an address;
• a first memory unit for storing systematic data samples of a turbo codeword;
• a second memory unit coupled to the address generator and storing parity data samples of the turbo codeword;
• and
• a third memory unit coupled to the address generator and storing bit probability likelihood ratios of the systematic data samples,
• wherein the address is simultaneously provided to at least the first memory unit, the second memory unit and the third memory unit such that the first memory unit reads a systematic data sample based on the address, the second memory unit reads a parity data sample based on the address and the third memory unit reads a likelihood ratio sample based on the address;
• and
• wherein the address further forms the basis of a write address provided to the third memory unit.

A decoder for use in data control supporting high-speed MAP decoding, the decoder comprising:

• an address generator for generating an address;
• a first memory unit coupled to the address generator and storing systematic data samples of a turbo codeword;
• a second memory unit coupled to the address generator and storing parity data samples of a top code and a bottom code of the turbo codeword;
• a third memory unit coupled to the address generator and storing bit probability likelihood ratios of the systematic data samples;
• a fourth memory unit coupled to the address generator and storing a de-interleaver definition;
• and
• a multiplexer coupled to the address generator and the fourth memory unit and selecting between an output of the address generator and the fourth memory unit,
• wherein the address is simultaneously provided to at least the second memory unit and the fourth memory unit and an output of the multiplexer provides an address to the first memory unit and the third memory unit.