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US 7,127,651 B2Granted
Sampling rate converter for both oversampling and undersampling operation
AssigneeSTMicroelectronics S.r.l.
InventorPascal Urard
Life of this patent
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Abstract
A sampling rate converter includes a chain of identical cells connected in series. An input of a first cell of the chain receives input digital sampling values according to an input frequency. An output of the first cell then delivers output digital sampling values according to an output frequency. The input and output digital sampling values correspond to identical respective reconstruction curves, and the output frequency may be greater than or less than the input frequency. Each cell includes a storage element, two multipliers and two adders.
Claims20
A sampling rate converter comprising:
- a chain of N cells, N being an integer greater than or equal to unity, each cell having a first, a second, a third and a fourth input of digital values, and having a first, a second, a third and a fourth output of digital values;
- the first and second outputs of a cell other than a last cell of the chain, and the third and fourth inputs of the said cell being connected respectively to the first and second inputs of a next cell along the chain, and to the third and fourth outputs of the said next cell, the first and second outputs of the last cell of the chain being connected respectively to the third and fourth inputs of the said last cell, the first input of a first cell of the chain for receiving successive digital input sampling values according to an input frequency, the second input of the said first cell for receiving a zero value, the fourth output of the said first cell then delivering successive digital output sampling values according to an output frequency;
- each cell comprising two multipliers connected by first respective inputs to an element for storing multiplicative coefficients, and connected by respective outputs of the said multipliers to first inputs of two respective adders, outputs of the said adders being linked respectively to the second and fourth outputs of the said cell, and second inputs of the said multipliers being linked respectively to the first and third outputs of the said cell;
- second inputs of the two multipliers of each cell furthermore linked respectively to the first and third inputs of the said cell by first respective pathways each comprising one and the same specified number of first flip-flops connected in series and oriented towards the corresponding multiplier;
- and
- second inputs of the two adders of each cell linked respectively to the second and fourth inputs of the said cell by second respective pathways each comprising second flip-flops connected in series according to the said specified number and oriented towards the corresponding adder.
3 more elements
A sampling rate converter, comprising:
- a cell having first, second, third and fourth inputs and first, second, third and fourth outputs, comprising:
- an element storing multiplicative coefficients;
- two multipliers connected by first respective inputs to the element and connected by respective outputs to first inputs of two respective adders, outputs of the adders being linked respectively to the first and fourth cell outputs, and second inputs of the said multipliers being linked respectively to the second and third outputs of the said cell, the second inputs of the two multipliers further linked respectively to the second and third inputs of the said cell by first respective pathways each comprising at least one first flip-flop;
- and
- second inputs of the two adders of each cell linked respectively to the first and fourth inputs of the cell by second respective pathways each comprising at least one flip-flop.
2 more elements
A sampling rate converter, comprising:
- an input receiving a signal a first frequency;
- an output generating a signal at a second frequency;
- a mode selection input receiving a mode selection signal;
- a plurality of switchable signal processing paths interconnecting the input to the output and including a first selectable signal processing path for implementing an undersampling operation with respect to the received signal and a second signal processing path for implementing an oversampling operation with respect to the received signal;
- and
- a selection circuit responsive to the received mode selection signal to switch received signal processing through the converter to first signal processing path to generate the output signal as an undersampled signal or to the second signal processing path to generate the output signal as an oversampled signal.
3 more elements
Dependencies are inferred from the claim text.