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US 7,127,647 B1Granted
Apparatus, method, and system to allocate redundant components
AssigneeVirage Logic Corporation
InventorsYervant Zorian, Gevorg Torjyan
Life of this patent
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Abstract
In general, a method, apparatus, and system determine the allocation of the one or more redundant components while fault testing the memory. In an embodiment of an apparatus, one or more memories and one or more processors are located on a single chip. Each memory has one or more redundant components associated with that memory. The one or more redundant components include at least one redundant column. The one or more processors contain redundancy allocation logic having an algorithm. The algorithm determines the allocation of the one or more redundant components to repair one or more defects detected in the one or more memories while fault testing the memory.
Claims35
An apparatus, comprising:
- a first set of two or more memory arrays, each memory having one or more redundant components associated with that memory array, the one or more redundant components include at least one redundant column, the first set of two or more memory arrays are located on a single chip;
- and
- a first processor located on the single chip, the first processor containing redundancy allocation logic having a repair algorithm, the repair algorithm to determine and optimize the allocation of the one or more redundant components to repair one or more defects detected in the first set of two or more memory arrays while fault testing the two or more memory arrays, wherein the first processor couples to the first set of two or more memory arrays and the repair algorithm to make multiple passes through a first memory array under analysis until a successful repair of the first memory array is achieved, where each pass implements a repair sequence having at least one of 1) a different order of assigning repair components compared to a previous pass and 2) a different memory address order compared to the previous pass in analyzing the first memory array to repair the first memory array.
A method, comprising:
- detecting defective memory locations in a first set of two or more embedded memory arrays;
- allocating redundant components to repair the defective memory locations while fault testing the first set of two or more embedded memory arrays;
- optimizing allocation of the redundant components;
- performing multiple passes through a first memory array under analysis until a successful repair of the first memory array is achieved, where each pass implements a repair sequence having at least one of 1) a different order of assigning repair components compared to a previous pass and 2) a different memory address order compared to the previous pass in analyzing the first memory array to repair the first memory array;
- and
- performing the detecting and the allocating every time a first processor located on the same chip as the first set of two or more embedded memory arrays is powered up or reset.
3 more elements
A method, comprising:
- testing each of a first set of two or more embedded memory arrays on a chip for defects;
- allocating redundant components to substitute for the non-redundant components connected with the defects with a first processor;
- performing repairs on each embedded memory array if defects exist in that embedded memory array with the first processor;
- programming the repair information with the first processor into one or more registers located in each memory array without programming any non-volatile fuses;
- performing multiple passes through a first memory array under analysis until a successful repair of the first memory array is achieved, where each pass implements a repair sequence having at least one of 1) a different order of assigning repair components compared to a previous pass and 2) a different memory address order compared to the previous pass in analyzing the first memory array to repair the first memory array;
- and
- performing the repairs on the embedded memory array without communicating the testing for defects results to a component external to the chip.
4 more elements
An apparatus, comprising:
- means for detecting defective memory locations in a first embedded memory array;
- means for allocating redundant components to repair the defective memory locations prior to the failure results being exported to a component external to the single chip;
- means for performing multiple passes through the first memory array under analysis until a successful repair of the first memory array is achieved, where each pass implements a repair sequence having at least one of 1) a different order of assigning repair components compared to a previous pass and 2) a different memory address order compared to the previous pass in analyzing the first memory array to repair the first memory array;
- and
- means for performing the detecting and the allocating every time a first processor located on the same chip as the first set of two or more embedded memory array is powered up or reset.
2 more elements
A machine-readable medium that stores instructions, which when executed by a machine, cause the machine to perform operations comprising:
- testing a first embedded memory array on a chip for defects;
- allocating redundant components to substitute for the non-redundant components connected with the defects;
- performing repairs on the first embedded memory array if defects exist in that embedded memory;
- programming the repair information into one or more registers located in the first memory array without programming any non-volatile fuses;
- performing multiple passes through the first memory array under analysis until a successful repair is achieved, where each pass implements a repair sequence having at least one of 1) a different order of assigning repair components and 2) a different memory address order in analyzing the first memory to repair the first memory;
- and
- performing the repairs on the first embedded memory arrays without communicating the testing for defects results to a component external to the chip.
4 more elements
An apparatus, comprising:
- one or more memory arrays, each memory array having one or more redundant components associated with that memory, the one or more redundant components include at least one redundant column, the one or more memory arrays are located on a single chip;
- and
- a first processor located on the single chip, the first processor containing redundancy allocation logic having a repair algorithm, the repair algorithm to determine the allocation of the one or more redundant components to repair two or more defects detected in the two or more memory arrays prior to the failure results being exported to a component external to the single chip, the first processor to program the repair information into one or more registers located in each memory array without programming any fuses, wherein the first processor couples to the one or more memory arrays and the repair algorithm to make multiple passes through a first memory array under analysis until a successful repair is achieved, where each pass implements a repair sequence having at least one of 1) a different order of assigning repair components and 2) a different memory address order in analyzing the first memory to repair the first memory.
Dependencies are inferred from the claim text.