Single wire serial interface utilizing count of encoded clock pulses with reset

A method for controlling a device, the method comprising:

• accumulating a count of clock pulses encoded in a received signal;
• mapping the count of encoded clock pulses into a corresponding control state for the device;
• and
• resetting the count of encoded clock pulses to zero in response to the received signal being low for a period that exceeds a predetermined timeout value, the predetermined time being longer than a width of one of the encoded clock pulses.

A method for controlling a device, the method comprising:

• toggling an input signal to the device to encode a series of clock pulses with the number of clock pulses corresponding to a desired control state for the device;
• maintaining the input signal in a logical high state for a period equal to the duration in which the desired control state is to remain active shortened by a predefined timeout period, the predefined timeout period being longer than a width of one of the encoded clock pulses;
• and
• maintaining the input signal in a logical low state for a duration that exceeds the predefined timeout period to terminate the desired state.

A device that comprises:

• a core portion configured to support a series of control states, each control state defining a set of operational parameters for the device;
• a counter for accumulating a count of clock pulses encoded in a received signal;
• a circuit for mapping the count of encoded clock pulses into a corresponding control state;
• and
• a sensing circuit for resetting the count of encoded clock pulses to zero in response to the received signal being low for a period that exceeds a predetermined timeout value, the predetermined timeout value being longer than a width of one of the encoded clock pulses.

An interface for controlling a device, the interface comprising:

• a first circuit for accumulating a count of clock pulses encoded in a received signal, the received signal having a first level and a second level, the encoded clock pulses including a transition from the first level to the second level and a transition from the second level to the first level;
• a second circuit for mapping the count of encoded clock pulses into a corresponding control state for the device;
• and
• a third circuit for resetting the count of encoded clock pulses to zero in response to the received signal being at the first level for a period that exceeds a predetermined timeout value after a transition from the second level to the first level, the predetermined timeout value being longer than a width of one of the encoded clock pulses.