Method for entering circuit test mode
AssigneeCypress Semiconductor Corporation
InventorWarren Snyder
Life of this patent
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Abstract
A method for entering test mode of an integrated circuit device is disclosed. In one embodiment of the present invention, after a lockout period, a test controller generates a signal indicating the integrated circuit is willing to enter the test mode. After the signal, the test controller monitors a test interface during a predetermined period of time for a digital password. Then, in response to a valid password being received within the predetermined period, the test controller enters the test mode. In another embodiment, in addition to the above steps, in response to the valid password being received, the test controller generates an acknowledge signal. In one embodiment, the predetermined period of time takes place during a holdoff period after the lockout period. In another embodiment, the test interface is serial.
Claims22
A method for entering test mode of an integrated circuit under test, said method comprising:
- generating a power-on reset release signal;
- generating a synchronization pulse indicating said integrated circuit is willing to enter said test mode, said synchronization pulse output from said integrated circuit under test to an external controller coupled to said integrated circuit under test by a test interface;
- after said synchronization pulse, monitoring a test interface for a digital password, wherein said generating a synchronization pulse and said monitoring a test interface occur within an interval of time that begins with said power-on reset release signal and has a predetermined length;
- and
- entering said test mode in response to a valid password being received within said predetermined interval of time.
A method for entering test mode of an integrated circuit under test, said method comprising:
- after a lockout period, generating a synchronization pulse indicating said integrated circuit under test is willing to enter said test mode, said synchronization pulse output from said integrated circuit under test to an external controller coupled to said integrated circuit under test by a test interface;
- after said synchronization pulse, a test controller of said integrated circuit monitoring said test interface during a predetermined period of time for a digital password;
- and
- said test controller entering said test mode in response to a valid password being received within said predetermined period of time.
A method for entering test mode of an integrated circuit device comprising:
- upon voltage application to said integrated circuit, entering a lockout period while voltage ramps up;
- generating a power-on reset release signal at the end of said lockout period;
- during a first time interval that begins at the falling edge of said power-on reset release signal and has a first predetermined length, a test controller of said integrated circuit causing a synchronization pulse to be output over a serial test interface to an external controller coupled to said integrated circuit by said serial test interface, said pulse indicating said integrated circuit is willing to negotiate entry into said test mode;
- during a second time interval that begins at the end of said first time interval and has a second predetermined length, said test controller monitoring said serial test interface for a digital password;
- and
- in response to a valid password being received within said second time interval, said test controller entering said test mode.
Dependencies are inferred from the claim text.