Back to results
US 7,127,629 B2Granted
Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal
AssigneeIntel Corporation
InventorPete D. Vogt
Life of this patent
Estimating the term…
Abstract
A method and apparatus for redriving a data signal adjusts a sampling clock signal responsive to the data signal. An embodiment of an I/O cell may include a receiver to receive and redrive a data signal responsive to a sampling clock signal, and a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal.
Claims20
An I/O cell comprising:
- a receiver to receive and redrive a data signal responsive to a sampling clock signal;
- a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal;
- and
- a buffer coupled to the receiver to redrive the data signal responsive to a stable clock signal;
- wherein the buffer is capable of operating in either a redrive mode or an unsampled pass-through mode responsive to a mode signal.
2 more elements
A system comprising:
- an I/O cell comprising:
- a receiver to receive and redrive a data signal responsive to a sampling clock signal,
- a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal;
- and
- a buffer coupled to the receiver to redrive the data signal responsive to a stable clock signal;
- wherein the buffer is capable of operating in either a redrive mode or an unsampled pass-through mode responsive to a mode signal;
- and
- a memory controller coupled to the I/O cell.
5 more elements
A method comprising:
- receiving a data signal;
- generating a sampling clock signal responsive to the data signal;
- sampling the data signal responsive to the sampling clock signal;
- and
- redriving the data signal responsive to either the sampling clock signal or a stable clock signal depending on a mode signal.
2 more elements
A memory buffer comprising:
- a receiver to receive and redrive a data signal responsive to a sampling clock signal;
- a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal;
- a memory interface coupled to the receiver;
- and
- a compensation buffer coupled to the receiver to redrive the data signal responsive to a stable clock signal;
- wherein the receiver and compensation buffer are each capable of operating in either a redrive mode or an unsampled pass-through mode responsive to a mode signal.
3 more elements
A system comprising:
- a memory buffer comprising:
- a receiver to receive and redrive a data signal responsive to a sampling clock signal,
- a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal,
- a memory interface coupled to the receiver, and
- a compensation buffer coupled to the receiver to redrive the data signal responsive to a stable clock signal,
- wherein the receiver and compensation buffer are each capable of operating in either a redrive mode or an unsampled pass-through mode responsive to a mode signal;
- and
- a memory controller coupled to the memory buffer.
5 more elements
A memory module comprising:
- a receiver to receive and redrive a data signal responsive to a sampling clock signal;
- a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal;
- a compensation buffer coupled to the receiver to redrive the data signal responsive to a stable clock signal;
- and
- a memory device coupled to the receiver;
- wherein the receiver and compensation buffer are each capable of operating in either a redrive mode or an unsampled pass-through mode responsive to a mode signal.
3 more elements
A system comprising:
- a memory module comprising:
- a receiver to receive and redrive a data signal responsive to a sampling clock signal,
- a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal,
- a compensation buffer coupled to the receiver to redrive the data signal responsive to a stable clock signal, and
- a memory device coupled to the receiver,
- wherein the receiver and compensation buffer are each capable of operating in either a redrive mode or an unsampled pass-through mode responsive to a mode signal;
- and
- a memory controller coupled to the memory module.
5 more elements
Dependencies are inferred from the claim text.