Semiconductor integrated circuits, data transfer systems, and the method for data transfer
AssigneeKabushiki Kaisha Toshiba
InventorYoshio Kaneko
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit configured for connection to an external ROM includes a decryption code block storing a decryption code; a decoder circuit connected to the decryption code block and decrypting encrypted data such that the encrypted data can be stored in the external ROM, by utilizing the decryption code; a configuration circuit connected to the decoder circuit; an FPGA circuit connected to the configuration circuit, the circuit structure of the FPGA circuit determined by the configuration circuit; and an internal circuit connected to the FPGA circuit, the circuit operation of which is determined by the FPGA circuit.
Claims15
A semiconductor integrated circuit configured for connection to a first external ROM and a second external ROM, comprising:
- a first decryption code block storing a decryption code;
- a first decoder circuit connected to the first decryption code block and decrypting encrypted data stored in the first external ROM, by utilizing the decryption code in the first decryption code block;
- a configuration circuit connected to the first decoder circuit;
- an FPGA circuit connected to the configuration circuit, wherein the circuit structure of the FPGA circuit is determined by the configuration circuit;
- a second decryption code block connected to the configuration circuit and comprising a circuit structure, determined by the configuration circuit, for storing a decryption code;
- a second decoder circuit connected to the second decryption code block, wherein the second decoder circuit decrypts encrypted data stored in the second external ROM by using the decryption code in the second decryption code block;
- a CPU connected to the second decoder circuit, the CPU being operable in response to encrypted data stored in the second external ROM;
- and
- an internal circuit connected to the FPGA circuit and the CPU, the circuit operation of which is determined by the FPGA circuit and the CPU.
A data transfer system configured for connection to external ROMs, comprising:
- a first external ROM storing encrypted FPGA circuit design information;
- a first decryption code block storing a decryption code;
- a first decoder circuit connected to the first decryption code block, wherein the first decoder circuit decrypts encrypted data from the first external ROM by utilizing the decryption code in the first decryption code block;
- a configuration circuit connected to the first decoder circuit;
- an FPGA circuit connected to the configuration circuit, the circuit structure of the FPGA circuit being determined by the configuration circuit;
- a second external ROM storing encrypted CPU software design information;
- a second decryption code block connected to the configuration circuit and comprising a circuit structure, determined by the configuration circuit, for storing a decryption code;
- a second decoder circuit connected to the second decryption code block, wherein the second decoder circuit decrypts encrypted data stored in the second external ROM by using the decryption code in the second decryption code block;
- a CPU connected to the second decoder circuit, the CPU being operable in response to the CPU software design information stored in the second external ROM;
- and
- an internal circuit connected to the FPGA circuit and the CPU, the circuit operation of the internal circuit being determined by the FPGA circuit and the CPU.
Dependencies are inferred from the claim text.