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US 7,127,574 B2Granted
Method and apparatus for out of order memory scheduling
AssigneeIntel Corporation
InventorsHemant G. Rotithor, Randy B. Osborne, Nagi Aboulenein
Life of this patent
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Abstract
Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.
Claims42
A method for out of order read or write scheduling using at least one queue, comprising:
- sorting memory transactions into at least one queue;
- within at least one queue, sorting memory transactions by attributes including address and address mapping used by memory, processor priority and demand versus prefetch transaction type;
- scheduling memory transactions out of order in accordance with scheduling algorithms, wherein if a DRAM command of a later memory transaction is scheduled before the last DRAM command of an earlier memory transaction, the later memory transaction is considered scheduled out of order and wherein the entire at least one queue is considered while making scheduling decisions;
- accommodating page closing policy with no prior assumption being made about pages being in a particular page miss or page empty or page hit state;
- and
- making out of order selection at the time of DRAM command launch.
3 more elements
A machine readable medium having stored therein a plurality of machine readable instructions executable by a processor for out of order memory scheduling using at least one queue, comprising:
- instructions to sort memory transactions into at least one queue including address and address mapping used by memory, processor priority and demand versus prefetch transaction type;
- instructions to, within at least one queue, sorting memory transactions by attributes;
- instructions to schedule memory transactions out of order in accordance with scheduling algorithms, wherein if a DRAM command of a later transaction is scheduled before the last DRAM command of an earlier transaction, the later transaction is considered scheduled out of order and wherein the entire at least one queue is considered while making scheduling decisions;
- instructions to accommodate page closing policy with no prior assumption being made about pages being in a particular page miss or page empty or page hit state;
- and
- instructions to make out of order selection at the time of DRAM command launch.
3 more elements
An apparatus comprising:
- at least one queue associated with a memory bank for receiving memory transactions sorted by attributes including address and address mapping used by memory, processor priority and demand versus prefetch transaction type;
- a page table to store information related to memory transactions;
- and
- a comparator and selector for receiving unblocked memory transactions from at least one queue and receiving page table information to determined if the unblocked transaction is a page hit, page miss or page empty,
- wherein memory transactions are scheduled out of order in accordance with scheduling algorithms, the entire at least one queue is considered while making scheduling decisions, page closing policy accommodations are made with no prior assumption about pages being in a particular page miss or page empty or page hit state and out of order selections are made at the time of DRAM command launch.
2 more elements
A system comprising:
- a memory including a plurality of banks;
- and
- a memory controller operatively in communication with the memory;
- at least one queue associated with a memory bank for receiving memory transactions sorted by attributes including address and address mapping used by memory, processor priority and demand versus prefetch transaction type;
- a page table to store information related to memory transactions;
- and
- a comparator and selector for receiving unblocked memory transactions from at least one queue and receiving page table information to determined if the unblocked transaction is a page hit, page miss or page empty,
- wherein memory transactions are scheduled out of order in accordance with scheduling algorithms, the entire at least one queue is considered while making scheduling decisions, page closing policy accommodations are made with no prior assumption about pages being in a particular page miss or page empty or page hit state and out of order selections are made at the time of DRAM command launch.
5 more elements
Dependencies are inferred from the claim text.