Double buffered flash programming

A system, comprising:

• a register interface;
• a first flash bank coupled to the register interface;
• a processor coupled to the register interface;
• a memory coupled to the processor and configured to store program instructions executable to:
• write a first address and a first set of data to the register interface;
• write the first set of data from the register interface to the first flash bank using the first address;
• and
• write a second address and a second set of data to the register interface, wherein at least a portion of the writing the second address and the second set of data to the register interface is performed simultaneously with the writing the first set of data from the register interface to the first flash bank.

A system, comprising:

• a means for writing a first address and a first set of data to a register interface;
• a means for writing the first set of data from the register interface to a first flash bank using the first address;
• and
• a means for writing a second address and a second set of data to the register interface, wherein at least a portion of the writing the second address and the second set of data to the register interface is performed simultaneously with the writing the first set of data from the register interface to the first flash bank.

A computer readable memory medium comprising program instructions, wherein the program instructions are computer-executable to:

• write a first address and a first set of data to a register interface;
• write the first set of data from the register interface to a first flash bank using the first address;
• and
• write a second address and a second set of data to the register interface, wherein at least a portion of the writing the second address and the second set of data to the register interface is performed simultaneously with the writing the first set of data from the register interface to the first flash bank.

A method, comprising:

• writing a first address and a first set of data to a first register interface;
• writing a second address and a second set of data to a second register interface, wherein at least a portion of the second address and the second set of data is written to the second register interface simultaneously with writing the first address and the first set of data to the first register interface;
• writing the first set of data to a first flash bank;
• writing the second set of data to a second flash bank;
• and
• wherein at least a portion of the writing of the second set of data to the second flash bank is performed simultaneously with the writing the first set of data to the first flash bank.

A method, comprising:

• writing a first address and a first set of data to a register interface;
• writing the first set of data from the register interface to a first flash bank using the first address;
• writing a second address and a second set of data to the register interface, wherein at least a portion of the writing the second address and the second set of data to the register interface is preformed simultaneously with the writing the first set of data from the register interface to the first flash bank, wherein the register interface further comprises a first register interface coupled to the first flash bank and a second register interface coupled to a second flash bank;
• and
• writing a third address and a third set of data to the second register interface, wherein at least a portion of the third address and the third set of data is written to the second register interface simultaneously with writing the first set of data to the first register interface.