Coherency techniques for suspending execution of a thread until a specified memory access occurs

An apparatus comprising:

• a bus controller having a plurality of bus cycle information lines;
• programmable memory access detection logic coupled to a bus, said programmable memory access detection logic comprising a storage location to store a monitor address specified by an instruction and comparison logic having inputs coupled to said storage location and said plurality of bus cycle information lines and a comparison logic output;
• suspend logic responsive to a second instruction in said first thread to suspend said first thread;
• and
• resume logic responsive to said comparison logic output to resume said first thread.

A method comprising:

• performing a first bus transaction to eliminate ownership by other agents of a cache line associated with a monitor address specified by an instruction;
• asserting a signal to allow a modification of the cache line in response to a second bus transaction attempting to gain ownership of said cache line associated with the monitor address;
• suspending execution of a first thread of which the instruction is apart, in response to a second instruction;
• and
• resuming execution of said first thread in response to detection of a memory access to the monitor address.

A system comprising:

• a bus;
• a first processor having a first cache;
• and
• a second processor having a second cache, said second processor comprising:
• a monitor to monitor transactions from the first processor on the bus to detect a memory access to a monitor address specified by an instruction executed by said second processor,
• coherence logic to generate a bus transaction to prevent said first cache from owning a cache line associated with said monitor address, and
• thread suspension logic to suspend a first thread of which said instruction is a part until an access to said cache line associated with said monitor address occurs.

A method comprising:

• performing a first bus transaction to eliminate ownership by other agents of a cache line associated with a monitor address specified by an instruction being part of a first thread of instructions;
• attempting to gain ownership of the cache line associated with the monitor address;
• suspending execution of the first thread in response to a second instruction;
• and
• resuming execution of the first thread in response to detection of a memory access to the monitor address.