Caching of dynamic arrays

A cache memory device, comprising:

• a plurality of memory cells adapted for caching array data traffic separate from other data traffic;
• and
• at least one register adapted for storing access information for accessing at least one array cached in the plurality of memory cells, wherein the access information includes:
• an array ID for identifying an array of memory cells within the plurality of memory cells;
• array height information;
• array width information;
• and
• array stride information.

An electronic system, comprising:

• a main memory;
• a dynamic array cache memory device coupled to the main memory and adapted for caching array data;
• a general cache memory device coupled to the main memory and adapted for caching regular data;
• and
• a processor coupled to and adapted for communication with the main memory, the general cache memory device, and the dynamic array cache memory device.

An electronic system, comprising:

• a main memory;
• a dynamic array cache memory device coupled to the main memory and adapted for caching array data, the dynamic array cache memory device including:
• a plurality of memory cells;
• and
• at least one register adapted for storing array access information, including:
• a base address for identifying a contiguous region of memory storage within the main memory;
• and
• array information for boundary and memory offset calculations;
• a general cache memory device coupled to the main memory and adapted for caching regular data;
• and
• a processor coupled to and adapted for communication with the main memory, the general cache memory device, and the dynamic array cache memory device.

A cached dynamic array (CDA) system, comprising:

• a main memory;
• a dynamic array cache memory coupled to the main memory and adapted for caching array data;
• a data cache memory coupled to the main memory and adapted for caching regular data;
• an instruction cache memory coupled to the main memory and adapted for caching processor instructions;
• a processor coupled to and in communication with the general cache memory, the dynamic array cache memory;
• and the instruction cache memory;
• and
• a computer readable medium encoded with a compiled software program capable of being executed by the processor such that the processor is adapted for:
• allocating a region of allocated memory for storing array elements;
• allocating and initializing an array descriptor register, and obtaining a corresponding array handle to the array descriptor register;
• overlaying an access structure on the region of memory by associating a pointer to the memory region with the array descriptor register;
• and
• accessing array elements using indices and the array handle.

A cached dynamic array (CDA) system, comprising:

• a main memory;
• a dynamic array cache memory coupled to the main memory and adapted for caching array data;
• a general cache memory coupled to the main memory and adapted for caching regular data;
• a processor coupled to and in communication with the main memory, the general cache memory, and the dynamic array cache memory;
• and
• a computer readable medium encoded with a compiled software program capable of being executed on the processor such that the processor is adapted for accessing dynamic array elements and reading memory data on a hardware path separate from a path used for regular data traffic.

A method of prefetching array data in an electronic system, comprising:

• separating each dynamic array access from regular data traffic;
• caching each dynamic array access into a dynamic array cache;
• and
• speculatively loading data based on anticipated dynamic array accesses into the dynamic array cache.