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US 7,127,550 B1Granted
Multi-module simultaneous program, erase test, and performance method for flash memory
AssigneeSanDisk Corporation
InventorJason T. Lin
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for accessing modules on a flash memory package concurrently during testing are disclosed. According to one aspect of the present invention, a memory device for storing data includes a plurality of modules and a logic block. The plurality of modules each include a plurality of storage elements that hold the data. The logic block is arranged to enable the plurality of modules to be accessed in parallel, and is also arranged to enable the plurality of modules to be accessed serially.
Claims23
A memory device for storing data, the memory device comprising:
- a plurality of modules, the plurality of modules each including a plurality of storage elements, wherein the plurality of storage elements are arranged to hold the data;
- a logic block, the logic block being arranged to enable a first subset of the plurality of modules to be accessed in parallel, the logic block further being arranged to enable the first subset of the plurality of modules to be accessed serially, wherein the first subset of the plurality of modules includes a first module and a second module, the first module including a first storage element, the second module including a second storage element, the first storage element and the second storage element being included in the plurality of storage elements;
- and
- a signal source, the signal source being arranged to provide a signal including the data to at least one of the first storage element and the second storage element, wherein when the logic block enables the first subset of the plurality of modules to be accessed in parallel, the signal source provides the signal to the first storage element and the second storage element substantially concurrently and the signal source is in communication with a testing device to receive the signal from the testing device, the testing device having one or more test heads and a computing device.
1 more element
A computing system comprising:
- a host system, the host system including a testing system that has one or more test heads, the testing system being arranged to test the functionality of a memory card;
- a memory system in the memory card, the memory system being in communication with the host system, the memory system including a plurality of modules, the plurality of modules each including a non-volatile memory array that is arranged to hold data, the memory system further including a state machine, the state machine being arranged to enable a first subset of the plurality of modules to be accessed in parallel, the state machine further being arranged to enable the first subset of the plurality of modules to be accessed serially;
- and
- wherein the memory card is one selected from the group consisting of a CompactFlash card, a MultiMedia card, a Secure Digital card, a Memory Stick, and a SmartMedia card.
1 more element
A method for testing a memory system, the memory system including at least a first module, a second module, and a third module, the method comprising:
- enabling the first module and the second module but not the third module to be tested in parallel, wherein enabling the first module and the second module but not the third module to be tested in parallel includes configuring the first module and the second module but not the third module to process an instruction substantially concurrently, wherein the first module includes a first storage element, the second module includes a second storage element, and the third module includes a third storage element, and wherein the instruction is a program instruction and causing the first module and the second module but not the third module to process the instruction substantially concurrently includes causing the first storage element and the second storage element but not the third storage element to be programmed substantially concurrently;
- issuing the instruction to the first module and the second module;
- causing the first module and the second module but not the third module to process the instruction substantially concurrently;
- enabling the first module and the second module to be tested in series after causing the first module and the second module to process the instruction substantially concurrently, wherein enabling the first module and the second module to be tested in series includes configuring the first module to process a read instruction before the second module processes the read instruction;
- issuing the read instruction to the first module and the second module;
- reading contents of the first storage element;
- and
- reading contents of the second storage element after reading the contents of the first storage element.
5 more elements
A method for testing a memory system, the memory system including at least a first module and a second module, the method comprising:
- enabling the first module and the second module to be tested, wherein enabling the first module and the second module to be tested includes configuring the first module and the second module to process a first instruction substantially in parallel and to process a second instruction substantially in series;
- issuing the first instruction to the first module and the second module;
- causing the first module and the second module to process the first instruction substantially in parallel;
- issuing the second instruction to the first module and the second module;
- and
- causing the first module and the second module to process the second instruction substantially in series.
3 more elements
Dependencies are inferred from the claim text.