Method and system of a microprocessor subtraction-division floating point divider

A method of determining quotient digits comprising:

• calculating a carry-propagate form of a plurality of most significant bits to the right of the radix point of the unshifted partial remainder;
• and
• assigning a next quotient digit to be a whole number value of at least one of the most significant bits to the right of the radix point of the unshifted partial remainder
• wherein assigning a next quotient digit to be a whole number value of at least one of the most significant bits to the right of the radix point of the unshifted partial remainder further comprises assigning a next quotient digit to be the whole number value of one of a number of most significant bits selected from the following table based on the radix of the divider algorithm:
• Number of bits
• representing the next
• Radix
• quotient digit
• 2
• 1
• 4
• 2
• 8
• 3
• 16
• 4
• 32
• 5.

In a microprocessor implementing a subtraction division algorithm for determining a quotient of a floating point divide operation by iteratively subtracting divisor multiples from a partial remainder, each subtraction producing an unshifted partial remainder in carry-save form that is multiplied by the radix of the algorithm to obtain a next partial remainder, a method of determining quotient digits comprising:

• prescaling the divisor to be in the range:
• 1≦D<1+(1/R)
• where D is the divisor, and R is the radix of the floating point division logic;
• calculating a carry-propagate form of a plurality of most significant bits to the right of the radix point of the unshifted partial remainder;
• and
• assigning a next quotient digit to be a whole number value of at least one of the most significant bits to the right of the radix point of the unshifted partial remainder.

In a microprocessor implementing a subtraction division algorithm for determining a quotient of a floating point divide operation by iteratively subtracting divisor multiples from a partial remainder, each subtraction producing and unshifted partial remainder in carry-save form that is multiplied by the radix of the algorithm to obtain a next partial remainder, a method of determining quotient digits comprising:

• calculating a carry-propagate form of a plurality of most significant bits to the right of the radix point of the unshifted partial remainder;
• and
• assigning a next quotient digit from the set of possible quotient digits
• {−(R−1), −(R−2), . . . , −(R−N), −0,0,(R−N), . . . (R−2), (R−1), R}
• where R is the radix and N=R−1.

A microprocessor having a subtractive division (SD) cell comprising:

• a first adder logic having a first set of inputs coupled to divisor multiples and a second set of inputs coupled to a partial remainder from a previous SD cell, the first adder logic producing bits to the right of the radix point of a resultant in carry-save form and also producing a first carry-out of the resultant;
• a second adder logic coupled to a plurality of the most significant bits of the resultant, the second adder logic converting the plurality of most significant bits of the resultant to carry-propagate form and also producing a second carry-out of the conversion of the plurality of most significant bits of the resultant to carry-propagate form;
• and
• a decode logic coupled to the first carry-out, the second carry-out, and the plurality of most significant bits of the resultant in carry-propagate form, and wherein the decode logic selects the quotient digit to be the whole number value of the plurality of most significant bits to the right of the radix point of the resultant in carry-propagate form.

A microprocessor having a floating point unit comprising a subtractive division (SD) system that comprises a prescale unit coupled to a divisor and a dividend, and wherein the prescale unit scales the divisor and the dividend, and also calculates divisor multiples, the microprocessor having an SD cell comprising:

• a first adder logic having a first set of inputs coupled to the divisor multiples and a second set of inputs coupled to a partial remainder from a previous SD cell, the first adder logic producing bits to the right of the radix point of a resultant in carry-save form and also producing a first carry-out of the resultant;
• a second adder logic coupled to a plurality of the most significant bits of the resultant, the second adder logic converting the plurality of most significant bits of the resultant to carry-propagate form and also producing a second carry-out of the conversion of the plurality of most significant bits of the resultant to carry-propagate form;
• and
• a decode logic coupled to the first carry-out, the second carry-out, and the plurality of most significant bits of the resultant in carry-propagate form, and wherein the decode logic selects the quotient digit to be the whole number value of the plurality of most significant bits of the resultant in carry-propagate form when only one of the first and second carry-outs is asserted.

A microprocessor having a floating point unit comprising a subtractive division (SD) system that comprises a prescale unit coupled to a divisor and a dividend, and wherein the prescale unit scales the divisor and the dividend, and also calculates divisor multiples, the microprocessor having an SD cell comprising:

• a first adder logic having a first set of inputs coupled to the divisor multiples and a second set of inputs coupled to a partial remainder from a previous SD cell, the first adder logic producing bits to the right of the radix point of a resultant in carry-save form and also producing a first carry-out of the resultant;
• a second adder logic coupled to a plurality of the most significant bits of the resultant, the second adder logic converting the plurality of most significant bits of the resultant to carry-propagate form and also producing a second carry-out of the conversion of the plurality of most significant bits of the resultant to carry-propagate form;
• and
• a decode logic coupled to the first carry-out, the second carry-out, and the plurality of most significant bits of the resultant in carry-propagate form, and wherein the decode logic selects the quotient digit from the set
• {−(R−1), −(R−2), . . . , −(R−N), −0,0,(R−N), . . . , (R−2), (R−1), R}
• where R is the radix on N=R−1.

A microprocessor having a floating point unit comprising a subtractive division (SD) system that comprises a prescale unit coupled to a divisor and a dividend, and wherein the prescale unit scales the divisor and the dividend, and also calculates divisor multiples, the microprocessor having an SD cell comprising:

• a first adder logic having a first set of inputs coupled to the divisor multiples and a second set of inputs coupled to a partial remainder from a previous SD cell, the first adder logic producing bits to the right of the radix point of a resultant in carry-save form and also producing a first carry-out of the resultant;
• a second adder logic coupled to a plurality of the most significant bits of the resultant, the second adder logic converting the plurality of most significant bits of the resultant to carry-propagate form and also producing a second carry-out of the conversion of the plurality of most significant bits of the resultant to carry-propagate form;
• and
• a decode logic coupled to the first carry-out, the second carry-out, and the plurality of most significant bits of the resultant in carry-propagate form, and wherein the decode logic selects the quotient digit from the set
• {−3,−2,−1,−0,0,1,2,3,4}
• in a Radix-4 subtractive division system.

In a microprocessor, implementing a floating point division algorithm for determining a quotient of a floating point divide operation comprising at least one cell iteratively subtracting divisor multiples from a partial remainder, each subtraction producing a resultant that is multiplied by the radix of the algorithm to obtain a next partial remainder, a method of operating a cell of the a floating point division algorithm comprising

• calculating a carry-save form of a resultant, each digit of the resultant represented by a sum bit and a carry bit, and the calculating the carry-save form of the resultant also producing a first carry-out;
• calculating a carry-propagate form of a plurality most significant bits to the right of the radix point of the resultant, and the calculating the carry-propagate form also producing a second carry-out;
• and
• assigning a next quotient digit to be a value directly indicated by at least one of the most significant bits to the right of the radix point of the resultant multiplied by the radix if only one of the first and second carry-outs are asserted.

In a microprocessor implementing a floating point division algorithm for determining a quotient of a floating point divide operation comprising at least one cell iteratively subtracting divisor multiples from a partial remainder, each subtraction producing a resultant that is multiplied by the radix of the algorithm to obtain a next partial remainder, a method of operating a cell of the floating point division algorithm comprising:

• calculating a carry-save form of the resultant, each digit of the resultant represented by a sum bit and a carry bit, and the calculating the carry-save form of the resultant also producing a first carry-out;
• calculating a carry-propagate form of the most significant bits to the right of the radix point for a Radix-4 divider, and the calculating the carry-propagate form also producing a second carry-out;
• and
• assigning a next quotient digit to be a value directly indicated by at least one of the most significant bits to the right of the radix point of the resultant multiplied by the radix if only one of the first and second carry-outs are asserted.

In a microprocessor implementing a floating point division algorithm for determining a quotient of a floating point divide operation comprising at least one cell iteratively subtracting divisor multiples from a partial remainder, each subtraction producing a resultant that is multiplied by the radix of the algorithm to obtain a next partial remainder a method of operating a cell of the floating point division algorithm comprising:

• calculating a carry-save form of the resultant, each digit of the resultant represented by a sum bit and a carry bit, and the calculating the carry-save form of the resultant also producing a first carry-out;
• calculating a carry-propagate form of a plurality most significant bits to the right of the radix point of the resultant, and the calculating the carry-propagate form also producing a second carry-out;
• and
• assigning the next quotient digit to be a negative one's complement of at least one of the most significant bits to the right of the radix point of the resultant multiplied by the radix if neither of the first and second carry-outs are asserted.

In a microprocessor having a floating point division logic, a method of operating an iterative cell of the floating point division logic comprising:

• subtracting a divisor multiple from a partial remainder from a previous iterative cell to form a resultant;
• multiplying the resultant by a radix of the floating point division logic to obtain a partial remainder for the next iterative cell;
• and
• prescaling the divisor such that a whole number part of the partial remainder for the next iterative cell indicates a next quotient digit directly.