Clock and data recovery circuits utilizing digital delay lines and digitally controlled oscillators
AssigneeXilinx, Inc.
InventorLeonard W. Dieguez
Life of this patent
Estimating the term…
Abstract
Clock and data recovery (CDR) circuits that are fully digital. A data stream encoded with clocking information is passed through a tapped digital delay line. A phase and frequency detector coupled to the registered outputs of the tapped digital delay line determines the phase and frequency relationship between the recovered clock (DCO clock) and the transmit clock. A filter and control circuit then uses this information to generate a “servo” control signal, which is passed through a dither circuit and fed back to a digitally controlled oscillator (DCO). The circuit adjusts the DCO clock signal to match the transmit clock based on the value of this control signal.
Claims20
A clock and date recovery (CDR) circuit, comprising:
- a serial data input terminal providing a data stream that includes an encoded transmit clock signal;
- a delay line phase and frequency detector having a first input terminal coupled to the serial data input terminal, a DCO clock input terminal, and a plurality of output terminals;
- a filter and control circuit having a plurality of input terminals coupled to the plurality of output terminals of the delay line phase and frequency detector, a DCO clock input terminal, and an output terminal;
- a dither circuit having an input terminal coupled to the output terminal of the filter and control circuit, a DCO clock input terminal, and an output terminal;
- and
- a digitally controlled oscillator (DCO) having an input terminal coupled to the output terminal of the dither circuit, and further having an output terminal coupled to the DCO clock input terminal of the delay line phase and frequency detector, the DCO clock input terminal of the filter and control circuit, and the dither circuit.
A system, comprising:
- a first device having a serial data output terminal, the serial data output terminal being coupled to provide a data stream that includes an encoded transmit clock signal;
- and
- a second device having a serial data input terminal coupled to the serial data output terminal of the first device, the second device further comprising:
- a delay line phase and frequency detector having a first input terminal coupled to the serial data input terminal, a DCO clock input terminal, and a plurality of output terminals;
- a filter and control circuit having a plurality of input terminals coupled to the plurality of output terminals of the delay line phase and frequency detector, a DCO clock input terminal, and an output terminal;
- a dither circuit having an input terminal coupled to the output terminal of the filter and control circuit, a DCO clock input terminal, and an output terminal;
- and
- a digitally controlled oscillator (DCO) having an input terminal coupled to the output terminal of the dither circuit, and further having an output terminal coupled to the DCO clock input terminal of the delay line phase and frequency detector, the DCO clock input terminal of the filter and control circuit, and the DCO clock input terminal of the dither circuit.
Dependencies are inferred from the claim text.