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US 7,127,021 B2Granted
Interleaved pulse-extended phase detector
AssigneeExar Corporation
InventorsShin Chung Chen, Roubik Gregorian, Mir Bahram Ghaderi, Vincent Sing Tso
Life of this patent
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AssigneeExar Corporation
InventorsShin Chung Chen, Roubik Gregorian, Mir Bahram Ghaderi, Vincent Sing Tso
Estimating the term…
A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.
A phase detector for Non-Return-to-Zero (NRZ) data, comprising:
A phase detector for Non-Return-to-Zero (NRZ) data, comprising:
A phase detector for Non-Return-to-Zero (NRZ) data, comprising:
A method for detecting a phase for Non-Return-to-Zero (NRZ) data, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: the phase or…
Details of the phase-locked loop: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its…
Speed or phase control by the received code signals, the signals containing no special synchronisation information: using the transitions of the…
Automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or
Term ended 12 Jul 2024 (estimated)
Co-owned application Ser. No. 10/118,661, filed Apr. 8, 2002, entitled “Clock and Data Recovery Circuit for Return-to-Zero Data” also uses a modified Hogge detector, but for RZ data.
NOT APPLICABLE
NOT APPLICABLE
FIG. 1 is a diagram of a prior art Hogge phase detector producing pump-up and pump-down signals.
FIG. 2 is a timing diagram corresponding to the detector of FIG. 1.
FIG. 3 is a prior art Hogge detector producing two pump-up and two pump-down signals.
FIG. 1 shows a simple prior art Hogge phase detector using flip-flops 10 and 12 connected in series, with the first flip-flop being clocked by the clock signal and the second by the inverse of the clock signal. The data input and data output of the first flip-flop are provided to an exclusive-OR gate 14 which provides a pump-up signal for a charge pump in the phase detector, as is known in the art. A second exclusive-OR gate 16 has inputs connected to the outputs of the two flip-flops and provides a pump-down signal to the charge pump. FIG. 2 illustrates the timing of the signals of the circuit of FIG. 1, with the numbers 1–6 corresponding to the labeled signals in FIG. 1.
FIG. 2 is a modification of the circuit of FIG. 1 which is used to equalize the effects of unequaled duty cycles. This circuit provides four flip-flops 18, 20, 22 and 24 connected in series. Similarly, four exclusive-OR gates 26, 28, 30 and 32 are used to provided two different pump-up and pump-down signals. FIG. 4 shows the timing for the signals labeled 1–10 in FIG. 3. For a description of how the pump-up and pump-down signals are used, and other aspects of a Hogge phase detector, see previously referenced U.S. Pat. No. 4,535,459.
When a high-speed signal is provided to the architecture of FIG. 1 or FIG. 2, a number of difficulties arise. For example, even simple digital latches or the charge pumps fail to respond to narrow input pulses, resulting in erroneous detection or suffering non-linearities in the closed-loop responses. On the one hand, it is desirable to lengthen the time intervals between corrections for the latches to operate correctly. On the other hand, it is desirable to extend the phase detector output pulses (the pump-up and pump-down signals) so that the charge pump can respond with desired linearity.