Clock recovery circuit with second order digital filter

A system for recovering data from a serial bit data stream, having a frequency, comprising:

• a means for regenerating at least one reclocking signal, having a frequency, to reclock the serial bit data stream;
• a means for determining whether the at least one reclocking signal is reclocking the serial bit data stream at an optimum point within the serial bit data stream;
• a means for storing the frequency offset if there is a frequency offset between the at least one reclocking signal and the serial bit data stream and if the serial bit data stream locks onto one value;
• and
• a means for generating at least one control signal to adjust the phase of the frequency of the at least one reclocking signal to reclock at substantially near the optimum point.

A clock recovery circuit comprising:

• a clock recovery loop filter comprising a second order filter;
• wherein said clock recovery loop filter is adaptable to determine whether a reclocking signal is reclocking a stream of data at an optimum location;
• and
• wherein said second order filter is adaptable to track the frequency offset if there is a frequency offset between the stream of data and the reclocking signal and if the stream of data locks onto one value.

A circuit for recovering data from a serial bit stream having a frequency with a phase comprising:

• a de-serializer configured for reclocking the serial bit stream using at least one reclocking signal, having a frequency with a phase, and de-serializing the serial bit stream into at least two bit streams, the at least two bit streams comprising a first bit stream representing data values from the serial bit stream and a second bit stream representing transition points of the serial bit stream;
• a clock recovery loop filter coupled with the deserializer, configured for determining whether the de-serializer is reclocking the serial bit data stream at an optimum location and generating at least one control signal to adjust the phase of the frequency of the at least one reclocking signal if the de-serializer is not reclocking the serial bit data stream at the optimum location, wherein the clock recovery loop filter comprises a second order filter;
• and
• a phase interpolator coupled with the clock recovery loop filter and the de-serializer, configured for generating the at least one reclocking signal in accordance with the at least one control signal.