Digital filter for reducing voltage peaks
AssigneeKoninklijke Philips Electronics N.V.
InventorsXavier David Bonafos, Jean-Michel Tanguy
Life of this patent
Estimating the term…
Loading patent…
AssigneeKoninklijke Philips Electronics N.V.
InventorsXavier David Bonafos, Jean-Michel Tanguy
Estimating the term…
The present invention relates to a digital filter suitable for receiving a digital input signal (INPUT(G)) comprising a voltage peak also known as glitch (G). It is characterized in that it comprises: a delay line (T) adapted to produce a delayed digital input signal (INPUT(G)+Δt), rising edge (PD) and falling edge (ND) detectors adapted to produce rising (P) and falling (N) edge indicator signals respectively from the delayed digital input signal (INPUT(G)+Δt), first (M1) and second (M2) mixing means adapted to produce rising (P′) and falling (N′) edge filter indicator signals respectively from said digital input signal (INPUT(G)) and said rising (P) and falling (N) edge indicator signals respectively, third mixing means (M3) adapted to produce a digital output signal (OUTPUT) without a glitch from the rising edge filter indicator signal (P′) and from the falling edge filter indicator signal (N′).
A digital filter suitable for receiving a digital input signal (INPUT(G)), comprising a rising edge detector (PD), a falling edge detector (ND), a delay line (T) adapted to delay said digital input signal (INPUT(G)) and to produce a delayed digital input signal (INPUT(G)+Δt), said digital input signal (INPUT(G)) comprising a voltage peak also known as glitch, wherein:
A method of filtering a digital signal (INPUT(G)) comprising a glitch, the method comprises the steps of:
Dependencies are inferred from the claim text.